ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 558

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AT32UC3A
Note that this interrupt is generated even if the clock is frozen by the FRZCLK bit.
• EORSM: End of Resume Interrupt Flag
Set by hardware when the USB controller detects a valid “End of Resume” signal initiated by the host. This triggers a USB
interrupt if EORSME = 1.
Shall be cleared by software (by setting the EORSMC bit) to acknowledge the interrupt.
• UPRSM: Upstream Resume Interrupt Flag
Set by hardware when the USB controller sends a resume signal called “Upstream Resume”. This triggers a USB interrupt
if UPRSME = 1.
Shall be cleared by software (by setting the UPRSMC bit) to acknowledge the interrupt (USB clock inputs must be enabled
before).
• EPXINT, X in [0..6]: Endpoint X Interrupt Flag
Set by hardware when an interrupt is triggered by the endpoint X (UESTAX, UECONX). This triggers a USB interrupt if
EPXINTE = 1.
Cleared by hardware when the interrupt source is serviced.
• DMAXINT, X in [1..6]: DMA Channel X Interrupt Flag
Set by hardware when an interrupt is triggered by the DMA channel X. This triggers a USB interrupt if DMAXINTE = 1.
Cleared by hardware when the UDDMAX_STATUS interrupt source is cleared.
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