ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 529
ATEVK1105
Manufacturer Part Number
ATEVK1105
Description
KIT EVAL FOR AT32UC3A0
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1105.pdf
(28 pages)
Specifications of ATEVK1105
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A0512
Processor Series
AVR
Data Bus Width
32 bit
Interface Type
USART, TWI, USB, SPI, Ethernet
Operating Supply Voltage
3.3 V
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A0512
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A0
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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- Download datasheet (20Mb)
30.7.4
Figure 30-30. Example of DMA Chained List
32058J–AVR32–04/11
USB DMA Channel X Registers
(Current Transfer Descriptor)
Next Descriptor Address
Memory Area
Data Buffer 1
Data Buffer 2
Data Buffer 3
HSB Address
USB DMA Operation
Control
Status
USB packets of any length may be transferred when required by the USB controller. These
transfers always feature sequential addressing. These two characteristics mean that in case of
high USB controller throughput, both HSB ports will benefit from “incrementing burst of unspeci-
fied length” since the average access latency of HSB slaves can then be reduced.
The DMA uses word “incrementing burst of unspecified length” of up to 256 beats for both data
transfers and channel descriptor loading. A burst may last on the HSB busses for the duration of
a whole USB packet transfer, unless otherwise broken by the HSB arbitration or the HSB 1 kbyte
boundary crossing.
Packet data HSB bursts may be locked on a DMA buffer basis for drastic overall HSB bus band-
width performance boost with paged memories. This is because these memories row (or bank)
changes, which are very clock-cycle consuming, will then likely not occur or occur once instead
of dozens of times during a single big USB packet DMA transfer in case other HSB masters
address the memory. This means up to 128 words single cycle unbroken HSB bursts for bulk
pipes/endpoints and 256 words single cycle unbroken bursts for isochronous pipes/endpoints.
This maximal burst length is then controlled by the lowest programmed USB pipe/endpoint size
(PSIZE/EPSIZE) and DMA channel byte length (CH_BYTE_LENGTH).
The USB controller average throughput may be up to nearly 1.5 Mbyte/s. Its average access
latency decreases as burst length increases due to the 0 wait-state side effect of unchanged
pipe/endpoint. Word access allows reducing the HSB bandwidth required for the USB by 4 com-
pared to native byte access. If at least 0 wait-state word burst capability is also provided by the
other DMA HSB bus slaves, each of both DMA HSB busses need less than 1.1% bandwidth
allocation for full USB bandwidth usage at 33 MHz, and less than 0.6% at 66 MHz.
Next Descriptor Address
Transfer Descriptor
HSB Address
Control
Next Descriptor Address
Transfer Descriptor
HSB Address
Control
Next Descriptor Address
Transfer Descriptor
HSB Address
Control
AT32UC3A
NULL
529
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