ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 402

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

27.6.9.3
27.6.9.4
Figure 27-36. Access to Non-sequential Data within the Same Page
32058J–AVR32–04/11
A[2], A1, A0
CLK_SMC
A[25:3]
D[7:0]
NRD
NCS
Page Mode Restriction
Sequential and Non-sequential Accesses
The page mode is not compatible with the use of the NWAIT signal. Using the page mode and
the NWAIT signal may lead to unpredictable behavior.
If the chip select and the MSB of addresses as defined in
rent access lies in the same page as the previous one, and no page break occurs.
Using this information, all data within the same page, sequential or not sequential, are accessed
with a minimum access time (t
page mode, with 8-byte pages. Access to D1 causes a page access with a long access time
(t
access time (t
If the MSB of addresses are different, the SMC performs the access of a new page. In the same
way, if the chip select is different from the previous access, a page break occurs. If two sequen-
tial accesses are made to the page mode memory, but separated by an other internal or external
peripheral access, a page break occurs on the second access because the chip select of the
device was deasserted between both accesses.
pa
). Accesses to D3 and D7, though they are not sequential accesses, only require a short
NCS_RD_PULSE
sa
).
A1
sa
).
D1
Figure 27-36
Page address
NRD_PULSE
A3
illustrates access to an 8-bit memory device in
D3
Table 27-5
NRD_PULSE
are identical, then the cur-
A7
AT32UC3A
D7
402