ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 525

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

30.7.3.9
30.7.3.10
32058J–AVR32–04/11
Management of Control Pipes
Management of IN Pipes
interrupt (HWUPI). If the non-idle bus state corresponds to an Upstream Resume (K state), the
Upstream Resume Received interrupt (RXRSMI) is raised. The firmware has to generate a
Downstream Resume within 1 ms and for at least 20 ms by setting the RESUME bit. It is manda-
tory to set SOFE before setting RESUME to enter the Ready state, else RESUME will have no
effect.
A control transaction is composed of three stages:
The firmware has to change the pipe token according to each stage.
For the control pipe, and only for it, each token is assigned a specific initial data toggle
sequence:
IN packets are sent by the USB device controller upon IN requests from the host. All the data
can be read by the firmware which acknowledges or not the bank when it is empty.
The pipe must be configured first.
When the host requires data from the device, the firmware has to select beforehand the IN
request mode with the INMODE bit:
The generation of IN requests starts when the pipe is unfrozen (PFREEZE = 0).
The RXINI bit is set by hardware at the same time as FIFOCON when the current bank is full.
This triggers a PXINT interrupt if RXINE = 1.
RXINI shall be cleared by software (by setting the RXINIC bit) to acknowledge the interrupt, what
has no effect on the pipe FIFO.
The firmware then reads from the FIFO and clears the FIFOCON bit to free the bank. If the IN
pipe is composed of multiple banks, this also switches to the next bank. The RXINI and FIFO-
CON bits are updated by hardware in accordance with the status of the next bank.
RXINI shall always be cleared before clearing FIFOCON.
The RWALL bit is set by hardware when the current bank is not empty, i.e. the software can read
further data from the FIFO.
•SETUP;
•Data (IN or OUT);
•Status (OUT or IN).
•SETUP: Data0;
•IN: Data1;
•OUT: Data1.
•when INMODE is cleared, the USB controller will perform (INRQ + 1) IN requests before
•when INMODE is set, the USB controller will perform IN requests endlessly when the pipe is
freezing the pipe;
not frozen by the firmware.
AT32UC3A
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