R0K572115S000BE Renesas Electronics America, R0K572115S000BE Datasheet
R0K572115S000BE
Specifications of R0K572115S000BE
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R0K572115S000BE Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7211 Group 32 Hardware Manual Renesas 32-Bit ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip ...
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This LSI is an RISC (Reduced Instruction Set Computer) microcomputer which includes a Renesas Technology-original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be ...
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Examples The notation used for register names, bit names, numbers, and symbols in this manual is described below. (1) Registers The style (register name)_(channel number) is used in cases where the same or a similar function is implemented on ...
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Notation in bit figures and tables describing arrangements of bits Each register description includes a figure that illustrates the arrangement of bits and a table that describes the meanings of settings in the bits. (1) Bit Indicates the bit ...
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Rev. 3.00 Mar. 04, 2009 Page viii of xxiv REJ09B0344-0300 ...
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Section 1 Overview..................................................................................................1 1.1 SH7211 Features.................................................................................................................... 1 1.2 Block Diagram ....................................................................................................................... 7 1.3 Pin Arrangement .................................................................................................................... 8 1.4 Pin Functions ......................................................................................................................... 9 Section 2 CPU........................................................................................................15 2.1 Register Configuration......................................................................................................... 15 2.1.1 General Registers .................................................................................................... 15 2.1.2 Control Registers .................................................................................................... 16 2.1.3 ...
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Mode 0 (MCU Extension Mode 0) ......................................................................... 57 3.3.2 Mode 1 (MCU Extension Mode 1) ......................................................................... 57 3.3.3 Mode 2 (MCU Extension Mode 2) ......................................................................... 57 3.3.4 Mode 3 (Single Chip Mode) ................................................................................... 57 3.4 Address Map ........................................................................................................................ 58 ...
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Interrupt Sources..................................................................................................... 90 5.5.2 Interrupt Priority Level ........................................................................................... 91 5.5.3 Interrupt Exception Handling.................................................................................. 92 5.6 Exceptions Triggered by Instructions .................................................................................. 93 5.6.1 Types of Exceptions Triggered by Instructions ...................................................... 93 5.6.2 Trap Instructions ..................................................................................................... 94 5.6.3 Slot Illegal Instructions ...
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Save and Restore Operations after Saving to All Banks....................................... 138 6.8.4 Register Bank Exception ...................................................................................... 139 6.8.5 Register Bank Error Exception Handling ............................................................. 139 6.9 Data Transfer with Interrupt Request Signals .................................................................... 140 6.9.1 Handling Interrupt Request Signals as ...
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Address Map ......................................................................................................... 179 8.3.2 Setting Operating Modes ...................................................................................... 180 8.4 Register Descriptions ......................................................................................................... 182 8.4.1 Common Control Register (CMNCR) .................................................................. 183 8.4.2 CSn Space Bus Control Register (CSnBCR ..................................... 186 8.4.3 CSn Space ...
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Transfer Flow........................................................................................................ 327 9.4.2 DMA Transfer Requests ....................................................................................... 329 9.4.3 Channel Priority.................................................................................................... 333 9.4.4 DMA Transfer Types............................................................................................ 336 9.4.5 Number of Bus Cycles and DREQ Pin Sampling Timing .................................... 345 9.5 Usage Note......................................................................................................................... 349 9.5.1 Half-End Flag Setting and ...
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Timer Cycle Buffer Register (TCBR)................................................................... 431 10.3.28 Timer Interrupt Skipping Set Register (TITCR) ................................................... 431 10.3.29 Timer Interrupt Skipping Counter (TITCNT)....................................................... 433 10.3.30 Timer Buffer Transfer Set Register (TBTER) ...................................................... 434 10.3.31 Timer Dead Time Enable Register (TDER).......................................................... 436 ...
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TCNT2 Write and Overflow/Underflow Contention in Cascade Connection ...... 558 10.7.13 Counter Value during Complementary PWM Mode Stop .................................... 560 10.7.14 Buffer Operation Setting in Complementary PWM Mode ................................... 560 10.7.15 Reset Sync PWM Mode Buffer Operation and Compare ...
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Interrupts............................................................................................................................ 634 12.6 Usage Note......................................................................................................................... 635 12.6.1 Pin Status When the WDT Issues a Power-On Reset ........................................... 635 Section 13 Compare Match Timer (CMT)...........................................................637 13.1 Features.............................................................................................................................. 637 13.2 Register Descriptions ......................................................................................................... 638 13.2.1 Compare Match Timer Start Register (CMSTR) ...
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System Reset by WDTOVF Signal....................................................................... 663 14.5.4 Manual Reset in Watchdog Timer Mode.............................................................. 664 Section 15 Serial Communication Interface with FIFO (SCIF)..........................665 15.1 Features.............................................................................................................................. 665 15.2 Input/Output Pins............................................................................................................... 667 15.3 Register Descriptions ......................................................................................................... 668 15.3.1 Receive Shift Register (SCRSR) ...
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I C Bus Mode Register (ICMR)............................................................................ 734 2 16.3 Bus Interrupt Enable Register (ICIER) ........................................................... 736 2 16.3 Bus Status Register (ICSR)............................................................................. 738 16.3.6 Slave Address Register (SAR) .............................................................................. 741 2 16.3 ...
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Example of ADDR Auto-Clear Function.............................................................. 788 17.5 Interrupt Sources and DMAC Transfer Requests .............................................................. 790 17.6 Definitions of A/D Conversion Accuracy.......................................................................... 791 17.7 Usage Notes ....................................................................................................................... 793 17.7.1 Relationship of AVcc and AVss to VccQ and VssQ ............................................ 793 ...
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Port A Port Registers H, L (PAPRH, PAPRL) ..................................................... 868 20.2 Port B ................................................................................................................................. 870 20.2.1 Register Descriptions ............................................................................................ 871 20.2.2 Port B Data Registers H, L (PBDRH, PBDRL).................................................... 871 20.2.3 Port B Port Registers H, L (PBPRH, PBPRL) ...
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Supplementary Information ............................................................................................... 949 21.8.1 Specifications of the Standard Serial Communications Interface in Boot Mode.. 949 21.8.2 Areas for Storage of the Procedural Program and Data for Programming............ 979 21.9 Programmer Mode ............................................................................................................. 986 Section 22 On-Chip RAM ...................................................................................987 ...
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H-UDI Interrupt .................................................................................................. 1017 24.5 Usage Notes ..................................................................................................................... 1018 Section 25 WAVE Interface (WAVEIF) ...........................................................1019 25.1 Features............................................................................................................................ 1019 25.2 Input/Output Pins ............................................................................................................. 1019 Section 26 List of Registers ...............................................................................1021 26.1 Register Addresses (by functional module, in order of the ...
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Main Revisions for This Edition .......................................................................1149 Index ...............................................................................................................1161 Rev. 3.00 Mar. 04, 2009 Page xxiv of xxiv REJ09B0344-0300 ...
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SH7211 Features This LSI is a single-chip RISC microprocessor that integrates a Renesas Technology original RISC CPU core with peripheral functions required for system configuration. The CPU in this LSI has a RISC-type (Reduced Instruction Set Computer) instruction set ...
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Table 1.1 SH7211 Features Items Specification • CPU Renesas Technology original SuperH architecture • Compatible with SH-1 and SH-2 at object code level • 32-bit internal data bus • Support of an abundant register-set ⎯ Sixteen 32-bit general registers ⎯ ...
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Items Specification • ROM cache Instruction/data separation system • Instruction prefetch cache: Full/set associative • Instruction prefetch miss cache: Full/set associative • Data cache: Full/set associative • Line size: 16 bytes • Hardware prefetch function (continuous/branch prefetch) • Interrupt controller ...
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Items Specification • Direct memory access Eight channels; external request available for four of them controller (DMAC) • Can be activated by on-chip peripheral modules • Burst mode and cycle steal mode • Intermittent mode available (16 and 64 cycles ...
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Items Specification • Multi-function timer Maximum 16 lines of pulse input/output and 3 lines of pulse input pulse unit 2 (MTU2) based on six channels of 16-bit timers • 21 output compare and input capture registers • Input capture function ...
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Items Specification • bus interface 3 One channel (IIC3) • Master mode and slave mode supported • I/O ports Input or output can be selected for each bit • A/D converter (ADC) 12-bit resolution • Eight input ...
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Block Diagram SH-2A CPU core ROM On-chip ROM Cache Bus state controller (BSC) Port External bus input/output External bus width mode input Pin function controller I/O ports generator (CPG) (PFC) Port General input/output Clock mode input High-performance Power-down user ...
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Pin Arrangement 108 107106 105 104 103102 101 100 PB22/AUDSYNC/RXD2/TCLKD/DACK2 109 PB23/AUDCK/TXD2/TCLKC/DREQ2 ...
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Pin Functions Table 1.2 lists functions of each pin. Table 1.2 Pin Functions Classification Symbol Power supply Vcc Vss VccQ VssQ PLLVcc PLLVss Clock EXTAL XTAL CK I/O Name Function I Power supply Power supply pins. All the Vcc ...
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Classification Symbol Operating mode MD1, MD0 control MD_CLK2, MD_CLK0 FWE ASEMD TESTMD RES System control MRES WDTOVF BREQ BACK Rev. 3.00 Mar. 04, 2009 Page 10 of 1168 REJ09B0344-0300 I/O Name Function I Mode set Sets the operating mode. Do ...
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Classification Symbol Interrupts NMI IRQ7 to IRQ0 IRQOUT Address bus A25 to A0 Data bus D15 to D0 CS7 to CS0 Bus control RD RD/ WAIT WE0 WE1 I/O Name Function I Non-maskable Non-maskable interrupt request pin. interrupt ...
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Classification Symbol DQMLL Bus control DQMLU RASL CASL CKE REFOUT Direct memory DREQ3 to access controller DREQ0 (DMAC) DACK3 to DACK0 TEND1, TEND0 O Multi-function TCLKA, timer pulse unit TCLKB, 2 (MTU2) TCLKC, TCLKD TIOC0A, TIOC0B, TIOC0C, TIOC0D TIOC1A, TIOC1B ...
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Classification Symbol Multi-function TIOC4A, timer pulse unit TIOC4B, 2 (MTU2) TIOC4C, TIOC4D TIC5U, TIC5V, TIC5W POE8, POE3, Port output POE1, POE0 enable 2 (POE2) POE7, POE4 Multi-function TIOC3AS, timer pulse unit TIOC3BS, 2S (MTU2S) TIOC3CS, TIOC3DS TIOC4AS, TIOC4BS, TIOC4CS, TIOC4DS ...
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Classification Symbol A/D converter AVss (ADC) AVREFVss D/A converter DA1, DA0 (DAC) I/O ports PA25 to PA0 PB30 to PB0 PD15 to PD0 PF1, PF0 User debugging TCK interface TMS (H-UDI) TDI TDO TRST Advanced user AUDATA3 to debugger (AUD) ...
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Register Configuration The register set consists of sixteen 32-bit general registers, four 32-bit control registers, and four 32-bit system registers. 2.1.1 General Registers Figure 2.1 shows the general registers. The sixteen 32-bit general registers are numbered R0 to R15. ...
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Control Registers The control registers consist of four 32-bit registers: the status register (SR), the global base register (GBR), the vector base register (VBR), and the jump table base register (TBR). The status register indicates instruction processing states. The ...
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Initial Value Bit Bit Name — All — All — — I[3:0] 1111 3, 2 — All 0 1 ...
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System Registers The system registers consist of four 32-bit registers: the high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). MACH and MACL store the results of multiply or ...
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Register Banks For the nineteen 32-bit registers comprising general registers R0 to R14, control register GBR, and system registers MACH, MACL, and PR, high-speed register saving and restoration can be carried out using a register bank. The register contents ...
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Data Formats 2.2.1 Data Format in Registers Register operands are always longwords (32 bits). If the size of memory operand is a byte (8 bits word (16 bits changed into a longword by expanding the ...
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Immediate Data Format Byte (8-bit) immediate data is located in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data. Immediate data accessed by the TST, AND, ...
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Instruction Features 2.3.1 RISC-Type Instruction Set Instructions are RISC type. This section details their functions. (1) 16-Bit Fixed-Length Instructions Basic instructions have a fixed length of 16 bits, improving program code efficiency. (2) 32-Bit Fixed-Length Instructions The SH-2A additionally ...
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Delayed Branch Instructions With the exception of some instructions, unconditional branch instructions, etc., are executed as delayed branch instructions. With a delayed branch instruction, the branch is taken after execution of the instruction immediately following the delayed branch instruction. ...
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Table 2.4 T Bit SH-2A CPU Description T bit is set when R0 ≥ R1. CMP/GE R1,R0 The program branches to TRGET0 BT TRGET0 when R0 ≥ R1 and to TRGET1 BF TRGET1 when R0 < R1. T bit is ...
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Absolute Address When data is accessed by an absolute address, the absolute address value should be placed in the memory table in advance. That value is transferred to the register by loading the immediate data during the execution of ...
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Addressing Modes Addressing modes and effective address calculation are as follows: Table 2.8 Addressing Modes and Effective Addresses Addressing Instruction Mode Format Register direct Rn Register indirect @Rn Register indirect @Rn+ with post- increment Register indirect @-Rn with pre- ...
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Addressing Instruction Mode Format Register indirect @(disp:4, with Rn) displacement Register indirect @(disp:12, with Rn) displacement Indexed register @(R0,Rn) indirect GBR indirect @(disp:8, with GBR) displacement Effective Address Calculation The effective address is the sum of Rn and a 4-bit ...
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Addressing Instruction Mode Format Indexed GBR @(R0, GBR) The effective address is the sum of GBR value indirect TBR duplicate @@ indirect with (disp:8, displacement TBR) PC indirect with @(disp:8, displacement PC) Rev. 3.00 Mar. 04, 2009 Page 28 of ...
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Addressing Instruction Mode Format PC relative disp:8 disp:12 Rn Effective Address Calculation The effective address is the sum of PC value and the value that is obtained by doubling the sign- extended 8-bit displacement (disp). PC disp PC + disp ...
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Addressing Instruction Mode Format Immediate #imm:20 #imm:8 #imm:8 #imm:8 #imm:3 Rev. 3.00 Mar. 04, 2009 Page 30 of 1168 REJ09B0344-0300 Effective Address Calculation The 20-bit immediate data (imm) for the MOVI20 instruction is sign-extended Sign- extended imm ...
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Instruction Format The instruction formats and the meaning of source and destination operands are described below. The meaning of the operand depends on the instruction code. The symbols used are as follows: • xxxx: Instruction code • mmmm: Source ...
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Instruction Formats m format 15 0 xxxx mmmm xxxx xxxx nm format 15 0 xxxx nnnn xxxx mmmm md format 15 0 xxxx xxxx mmmm dddd Rev. 3.00 Mar. 04, 2009 Page 32 of 1168 REJ09B0344-0300 Source Destination Operand Operand ...
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Instruction Formats nd4 format 15 0 xxxx xxxx nnnn dddd nmd format 15 0 xxxx nnnn mmmm dddd nmd12 format 32 16 xxxx nnnn mmmm xxxx 15 0 xxxx dddd dddd dddd d format 15 0 xxxx xxxx dddd dddd ...
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Instruction Formats i format 15 0 xxxx xxxx iiii iiii ni format 15 0 xxxx nnnn iiii iiii ni3 format 15 0 xxxx xxxx nnnn x iii ni20 format 32 16 xxxx nnnn iiii xxxx 15 0 iiii iiii iiii ...
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Instruction Set 2.4.1 Instruction Set by Classification Table 2.10 lists the instructions according to their classification. Table 2.10 Classification of Instructions Operation Classification Types Code Data transfer 13 MOV MOVA MOVI20 MOVI20S MOVML MOVMU MOVRT MOVT MOVU NOTT PREF ...
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Operation Classification Types Code Arithmetic 26 ADD operations ADDC ADDV CMP/cond Comparison CLIPS CLIPU DIVS DIVU DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC MUL MULR MULS MULU NEG NEGC SUB SUBC SUBV Rev. 3.00 Mar. 04, 2009 Page ...
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Operation Classification Types Code Logic 6 AND operations NOT OR TAS TST XOR Shift 12 ROTL ROTR ROTCL ROTCR SHAD SHAL SHAR SHLD SHLL SHLLn SHLR SHLRn Branch BRA BRAF BSR BSRF JMP JSR RTS RTV/N Function ...
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Operation Classification Types Code System 14 CLRT control CLRMAC LDBANK LDC LDS NOP RESBANK Register restoration from register bank RTE SETT SLEEP STBANK STC STS TRAPA Bit 10 BAND manipulation BCLR BLD BOR BSET BST BXOR BANDNOT Bit NOT AND ...
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The table below shows the format of instruction codes, operation, and execution states. They are described by using this format according to their classification. Instruction Instruction Code Indicated in MSB ↔ Indicated by mnemonic. LSB order. [Legend] [Legend] OP.Sz SRC, ...
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Data Transfer Instructions Table 2.11 Data Transfer Instructions Instruction Instruction Code 1110nnnniiiiiiii imm → sign extension → Rn MOV #imm,Rn 1001nnnndddddddd (disp × PC) → sign MOV.W @(disp,PC),Rn 1101nnnndddddddd (disp × PC) → Rn MOV.L ...
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Instruction Instruction Code 0000nnnnmmmm0101 Rm → (R0 + Rn) MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0110 Rm → (R0 + Rn) MOV.L Rm,@(R0,Rn) 0000nnnnmmmm1100 (R0 + Rm) → MOV.B @(R0,Rm),Rn 0000nnnnmmmm1101 (R0 + Rm) → MOV.W @(R0,Rm),Rn 0000nnnnmmmm1110 (R0 + Rm) → Rn MOV.L ...
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Instruction Instruction Code MOV.W @(disp12,Rm),Rn 0011nnnnmmmm0001 0101dddddddddddd MOV.L @(disp12,Rm),Rn 0011nnnnmmmm0001 0110dddddddddddd 11000111dddddddd disp × → R0 MOVA @(disp,PC),R0 MOVI20 #imm20,Rn 0000nnnniiii0000 iiiiiiiiiiiiiiii MOVI20S #imm20,Rn 0000nnnniiii0001 iiiiiiiiiiiiiiii 0100mmmm11110001 R15-4 → R15, Rm → (R15) MOVML.L Rm,@-R15 0100nnnn11110101 (R15) ...
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Instruction Instruction Code 0000nnnn00111001 ~T → Rn MOVRT Rn 0000nnnn00101001 T → Rn MOVT Rn MOVU.B @(disp12,Rm),Rn 0011nnnnmmmm0001 1000dddddddddddd MOVU.W @(disp12,Rm),Rn 0011nnnnmmmm0001 1001dddddddddddd 0000000001101000 ~T → T NOTT 0000nnnn10000011 (Rn) → operand cache PREF @Rn 0110nnnnmmmm1000 Rm → swap lower ...
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Arithmetic Operation Instructions Table 2.12 Arithmetic Operation Instructions Instruction Instruction Code ADD Rm,Rn 0011nnnnmmmm1100 ADD #imm,Rn 0111nnnniiiiiiii ADDC Rm,Rn 0011nnnnmmmm1110 ADDV Rm,Rn 0011nnnnmmmm1111 CMP/EQ #imm,R0 10001000iiiiiiii CMP/EQ Rm,Rn 0011nnnnmmmm0000 CMP/HS Rm,Rn 0011nnnnmmmm0010 CMP/GE Rm,Rn 0011nnnnmmmm0011 CMP/HI Rm,Rn 0011nnnnmmmm0110 CMP/GT ...
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Instruction Instruction Code CLIPS.B Rn 0100nnnn10010001 CLIPS.W Rn 0100nnnn10010101 CLIPU.B Rn 0100nnnn10000001 CLIPU.W Rn 0100nnnn10000101 DIV1 Rm,Rn 0011nnnnmmmm0100 DIV0S Rm,Rn 0010nnnnmmmm0111 DIV0U 0000000000011001 DIVS R0,Rn 0100nnnn10010100 DIVU R0,Rn 0100nnnn10000100 DMULS.L Rm,Rn 0011nnnnmmmm1101 DMULU.L Rm,Rn 0011nnnnmmmm0101 DT Rn 0100nnnn00010000 EXTS.B Rm,Rn ...
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Instruction Instruction Code EXTU.B Rm,Rn 0110nnnnmmmm1100 EXTU.W Rm,Rn 0110nnnnmmmm1101 MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 MUL.L Rm,Rn 0000nnnnmmmm0111 MULR R0,Rn 0100nnnn10000000 MULS.W Rm,Rn 0010nnnnmmmm1111 MULU.W Rm,Rn 0010nnnnmmmm1110 NEG Rm,Rn 0110nnnnmmmm1011 NEGC Rm,Rn 0110nnnnmmmm1010 SUB Rm,Rn 0011nnnnmmmm1000 SUBC Rm,Rn 0011nnnnmmmm1010 SUBV ...
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Logic Operation Instructions Table 2.13 Logic Operation Instructions Instruction Instruction Code AND Rm,Rn 0010nnnnmmmm1001 AND #imm,R0 11001001iiiiiiii AND.B #imm,@(R0,GBR) 11001101iiiiiiii NOT Rm,Rn 0110nnnnmmmm0111 OR Rm,Rn 0010nnnnmmmm1011 OR #imm,R0 11001011iiiiiiii OR.B #imm,@(R0,GBR) 11001111iiiiiiii TAS.B @Rn 0100nnnn00011011 TST Rm,Rn 0010nnnnmmmm1000 TST ...
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Shift Instructions Table 2.14 Shift Instructions Instruction Instruction Code ROTL Rn 0100nnnn00000100 ROTR Rn 0100nnnn00000101 ROTCL Rn 0100nnnn00100100 ROTCR Rn 0100nnnn00100101 SHAD Rm,Rn 0100nnnnmmmm1100 SHAL Rn 0100nnnn00100000 SHAR Rn 0100nnnn00100001 SHLD Rm,Rn 0100nnnnmmmm1101 SHLL Rn 0100nnnn00000000 SHLR Rn 0100nnnn00000001 ...
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Branch Instructions Table 2.15 Branch Instructions Instruction Instruction Code BF label 10001011dddddddd BF/S label 10001111dddddddd BT label 10001001dddddddd BT/S label 10001101dddddddd BRA label 1010dddddddddddd BRAF Rm 0000mmmm00100011 BSR label 1011dddddddddddd BSRF Rm 0000mmmm00000011 JMP @Rm 0100mmmm00101011 JSR @Rm 0100mmmm00001011 ...
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System Control Instructions Table 2.16 System Control Instructions Instruction Instruction Code CLRT 0000000000001000 CLRMAC 0000000000101000 LDBANK @Rm,R0 0100mmmm11100101 LDC Rm,SR 0100mmmm00001110 LDC Rm,TBR 0100mmmm01001010 LDC Rm,GBR 0100mmmm00011110 LDC Rm,VBR 0100mmmm00101110 LDC.L @Rm+,SR 0100mmmm00000111 LDC.L @Rm+,GBR 0100mmmm00010111 LDC.L @Rm+,VBR 0100mmmm00100111 ...
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Instruction Instruction Code STC GBR,Rn 0000nnnn00010010 STC VBR,Rn 0000nnnn00100010 STC.L SR,@-Rn 0100nnnn00000011 STC.L GBR,@-Rn 0100nnnn00010011 STC.L VBR,@-Rn 0100nnnn00100011 STS MACH,Rn 0000nnnn00001010 STS MACL,Rn 0000nnnn00011010 STS PR,Rn 0000nnnn00101010 STS.L MACH,@-Rn 0100nnnn00000010 STS.L MACL,@-Rn 0100nnnn00010010 STS.L PR,@-Rn 0100nnnn00100010 TRAPA #imm 11000011iiiiiiii Notes: ...
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Bit Manipulation Instructions Table 2.17 Bit Manipulation Instructions Instruction BAND.B #imm3,@(disp12,Rn) BANDNOT.B #imm3,@(disp12,Rn) BCLR.B #imm3,@(disp12,Rn) BCLR #imm3,Rn BLD.B #imm3,@(disp12,Rn) BLD #imm3,Rn BLDNOT.B #imm3,@(disp12,Rn) BOR.B #imm3,@(disp12,Rn) BORNOT.B #imm3,@(disp12,Rn) BSET.B #imm3,@(disp12,Rn) BSET #imm3,Rn BST.B #imm3,@(disp12,Rn) BST #imm3,Rn Rev. 3.00 Mar. 04, ...
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Instruction BXOR.B #imm3,@(disp12,Rn) 2.5 Processing States The CPU has five processing states: reset, exception handling, bus-released, program execution, and power-down. Figure 2.6 shows the transitions between the states. Power-on reset from any state Interrupt source or DMA address error occurs ...
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Reset State In the reset state, the CPU is reset. There are two kinds of reset, power-on reset and manual reset. (2) Exception Handling State The exception handling state is a transient state that occurs when exception handling sources ...
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Section 3 MCU Operating Modes 3.1 Selection of Operating Modes This LSI has four MCU operating modes and three on-chip flash memory programming modes. The operating mode is determined by the setting of FWE, MD1, and MD0 pins. Table 3.1 ...
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Input/Output Pins Table 3.2 describes the configuration of operating mode related pin. Table 3.2 Pin Configuration Pin Name Input/Output MD0 Input MD1 Input FWE Input Rev. 3.00 Mar. 04, 2009 Page 56 of 1168 REJ09B0344-0300 Function Designates operating mode ...
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Operating Modes 3.3.1 Mode 0 (MCU Extension Mode 0) In this mode, CS0 space becomes external memory spaces with 16-bit bus width. 3.3.2 Mode 1 (MCU Extension Mode 1) In this mode, CS0 space becomes external memory spaces with ...
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Address Map The address map for the operating modes is shown in figure 3.1, 3.2. Modes 0 and 1 On-chip ROM disabled mode H'00000000 CS0 space H'03FFFFFF H'04000000 CS1 space H'07FFFFFF H'08000000 CS2 space H'0BFFFFFF H'0C000000 CS3 space H'0FFFFFFF ...
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Modes 0 and 1 On-chip ROM disabled mode H'00000000 H'00000000 H'0007FFFF H'00080000 CS0 space H'01FFFFFF H'02000000 H'03FFFFFF H'03FFFFFF H'04000000 H'04000000 CS1 space H'07FFFFFF H'07FFFFFF H'08000000 H'08000000 CS2 space H'0BFFFFFF H'0BFFFFFF H'0C000000 H'0C000000 CS3 space H'0FFFFFFF H'0FFFFFFF H'10000000 H'10000000 CS4 space ...
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Initial State in This LSI In the initial state of this LSI, some of on-chip modules are set in module standby state for saving power. When operating these modules, clear module standby state according to the procedure in section ...
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Section 4 Clock Pulse Generator (CPG) This LSI has a clock pulse generator (CPG) that generates an internal clock (Iφ), a peripheral clock (Pφ), a bus clock (Bφ), an MTU2S clock (Mφ), and an AD clock (Aφ). The CPG consists ...
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CK Crystal XTAL oscillator EXTAL MD_CLK2 MD_CLK0 FRQCR [Legend] FRQCR: Frequency control register MCLKCR: MTU2S clock frequency control register ACLKCR: AD clock frequency control register STBCR: Standby control register STBCR2: Standby control register 2 STBCR3: Standby control register 3 STBCR4: ...
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The clock pulse generator blocks function as follows: (1) PLL Circuit 1 PLL circuit 1 multiplies the input clock frequency from the CK pin The multiplication rate is set by the frequency control register. When ...
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Standby Control Circuit The standby control circuit controls the states of the clock pulse generator and other modules during clock switching, or sleep or software standby mode. (7) Frequency Control Register (FRQCR) The frequency control register (FRQCR) has control ...
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Input/Output Pins Table 4.1 lists the clock pulse generator pins and their functions. Table 4.1 Pin Configuration and Functions of the Clock Pulse Generator Pin Name Symbol Mode control pins MD_CLK0 MD_CLK2 Crystal input/output XTAL pins (clock input pins) ...
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Clock Operating Modes Table 4.2 shows the relationship between the combinations of the mode control pins (MD_CLK2 and MD_CLK0) and the clock operating modes. Table 4.3 shows the usable frequency ranges in the clock operating modes. Table 4.2 Clock ...
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Table 4.3 Relationship between Clock Operating Mode and Frequency Range PLL Frequency Multiplier Clock Operating FRQCR PLL PLL Mode Setting Circuit 1 Circuit 2 6 H'1000 On (× (×4) H'1001 On (× (×4) H'1003 On (× ...
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Register Descriptions The clock pulse generator has the following registers. Table 4.4 Register Configuration Register Name Frequency control register MTU2S clock frequency control register AD clock frequency control register 4.4.1 Frequency Control Register (FRQCR) FRQCR is a 16-bit readable/writable ...
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Initial Value Bit Bit Name 12 CKOEN 1 ⎯ 11, 10 All STC[1:0] 00 ⎯ R/W Description R/W Clock Output Enable Specifies whether a clock is output on the CK pin, or the CK pin ...
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Initial Value Bit Bit Name IFC[2:0] 000 3 RNGS PFC[2:0] 011 Rev. 3.00 Mar. 04, 2009 Page 70 of 1168 REJ09B0344-0300 R/W Description R/W Internal Clock (Iφ) Frequency Division Ratio These bits specify ...
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MTU2S Clock Frequency Control Register (MCLKCR) MCLKCR is an 8-bit readable/writable register. Only byte access can be used on MCLKCR. MCLKCR is initialized to H'43 only by a power-on reset. MCLKCR retains its previous value by a manual reset ...
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AD Clock Frequency Control Register (ACLKCR) ACLKCR is an 8-bit readable/writable register that can be accessed only in byte units. ACLKCR is only initialized to H' power-on reset, but retains its previous value by a manual reset ...
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Changing the Frequency The frequency of the internal clock (Iφ) and peripheral clock (Pφ) can be changed either by changing the multiplication rate of PLL circuit changing the division rates of divider. All of these are ...
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Changing the Division Ratio Counting by the WDT does not proceed if the frequency divisor is changed but the multiplier is not the initial state, IFC[2:0] = B'000 and PFC[2:0] = B'011. 2. Set the desired value ...
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Notes on Board Design 4.6.1 Note on Using an External Crystal Resonator Place the crystal resonator and capacitors CL1 and CL2 as close to the XTAL and EXTAL pins as possible. In addition, to minimize induction and thus obtain ...
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Figure 4.3 Note on Using a PLL Oscillation Circuit Rev. 3.00 Mar. 04, 2009 Page 76 of 1168 REJ09B0344-0300 Signal lines prohibited Power supply Vcc PLLVcc Vss PLLVss ...
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Section 5 Exception Handling 5.1 Overview 5.1.1 Types of Exception Handling and Priority Exception handling is started by sources, such as resets, address errors, register bank errors, interrupts, and instructions. Table 5.1 shows their priorities. When several exception handling sources ...
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Type Exception Handling Interrupt On-chip peripheral modules Instruction Trap instruction (TRAPA instruction) General illegal instructions (undefined code) Slot illegal instructions (undefined code placed directly after a delayed branch instruction* 3 instructions* , RESBANK instruction, DIVS instruction, and DIVU instruction) Notes: ...
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Exception Handling Operations The exception handling sources are detected and begin processing according to the timing shown in table 5.2. Table 5.2 Timing of Exception Source Detection and Start of Exception Handling Exception Source Reset Power-on reset Manual reset ...
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When exception handling starts, the CPU operates as follows: (1) Exception Handling Triggered by Reset The initial values of the program counter (PC) and stack pointer (SP) are fetched from the exception handling vector table (PC and SP are respectively ...
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Exception Handling Vector Table Before exception handling begins running, the exception handling vector table must be set in memory. The exception handling vector table stores the start addresses of exception service routines. (The reset exception handling table holds the ...
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Exception Sources Integer division exception (division by zero) Integer division exception (overflow) (Reserved by system) Trap instruction (user vector) External interrupts (IRQ), on-chip peripheral module interrupts* Note: * The vector numbers and vector table address offsets for each external interrupt ...
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Resets 5.2.1 Types of Reset A reset is the highest-priority exception handling source. There are two kinds of reset, power-on and manual. As shown in table 5.5, the CPU state is initialized in both a power-on reset and a ...
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Power-On Reset Power-On Reset by Means of RES Pin (1) When the RES pin is driven low, this LSI enters the power-on reset state. To reliably reset this LSI, the RES pin should be kept at the low level ...
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Power-On Reset Initiated by WDT When a setting is made for a power-on reset to be generated in the WDT’s watchdog timer mode, and WTCNT of the WDT overflows, this LSI enters the power-on reset state. In this case, ...
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Manual Reset Manual Reset by Means of MRES Pin (1) When the MRES pin is driven low, this LSI enters the manual reset state. To reset this LSI without fail, the MRES pin should be kept at the low ...
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Address Errors 5.3.1 Address Error Sources Address errors occur when instructions are fetched or data read or written, as shown in table 5.6. Table 5.6 Bus Cycles and Address Errors Bus Cycle Bus Type Master Instruction CPU fetch Data ...
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Address Error Exception Handling When an address error occurs, the bus cycle in which the address error occurred ends*. When the executing instruction then finishes, address error exception handling starts. The CPU operates as follows: 1. The exception service ...
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Register Bank Errors 5.4.1 Register Bank Error Sources (1) Bank Overflow In the state where saving has already been performed to all register bank areas, bank overflow occurs when acceptance of register bank overflow exception has been set by ...
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Interrupts 5.5.1 Interrupt Sources Table 5.7 shows the sources that start up interrupt exception handling. These are divided into NMI, user breaks, H-UDI, IRQ, and on-chip peripheral modules. Table 5.7 Interrupt Sources Type NMI User break H-UDI IRQ On-chip ...
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Interrupt Priority Level The interrupt priority order is predetermined. When multiple interrupts occur simultaneously (overlap), the interrupt controller (INTC) determines their relative priorities and starts processing according to the results. The priority order of interrupts is expressed as priority ...
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Interrupt Exception Handling When an interrupt occurs, its priority level is ascertained by the interrupt controller (INTC). NMI is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set ...
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Exceptions Triggered by Instructions 5.6.1 Types of Exceptions Triggered by Instructions Exception handling can be triggered by trap instructions, general illegal instructions, slot illegal instructions, and integer division exceptions, as shown in table 5.9. Table 5.9 Types of Exceptions ...
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Trap Instructions When a TRAPA instruction is executed, trap instruction exception handling starts. The CPU operates as follows: 1. The exception service routine start address which corresponds to the vector number specified in the TRAPA instruction is fetched from ...
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General Illegal Instructions When undefined code placed anywhere other than immediately after a delayed branch instruction (i.e delay slot) is decoded, general illegal instruction exception handling starts. The CPU handles general illegal instructions in the same way ...
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When Exception Sources Are Not Accepted When an address error, register bank error (overflow), or interrupt is generated immediately after a delayed branch instruction sometimes not accepted immediately but stored instead, as shown in table 5.10. When ...
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Stack Status after Exception Handling Ends The status of the stack after exception handling ends is as shown in table 5.11. Table 5.11 Stack Status After Exception Handling Ends Exception Type Address error Interrupt Register bank error (overflow) Register ...
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Exception Type General illegal instruction Integer division instruction Rev. 3.00 Mar. 04, 2009 Page 98 of 1168 REJ09B0344-0300 Stack Status Start address of general SP illegal instruction SR Start address of relevant SP integer division instruction SR 32 bits 32 ...
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Usage Notes 5.9.1 Value of Stack Pointer (SP) The value of the stack pointer must always be a multiple of four not, an address error will occur when the stack is accessed during exception handling. 5.9.2 ...
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Rev. 3.00 Mar. 04, 2009 Page 100 of 1168 REJ09B0344-0300 ...
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Section 6 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to process interrupt requests ...
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Figure 6.1 shows a block diagram of the INTC. IRQOUT NMI Input control IRQ7 to IRQ0 (Interrupt request) UBC (Interrupt request) H-UDI (Interrupt request) DMAC (Interrupt request) CMT (Interrupt request) BSC (Interrupt request) WDT (Interrupt request) MTU2 (Interrupt request) MTU2S ...
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Input/Output Pins Table 6.1 shows the pin configuration of the INTC. Table 6.1 Pin Configuration Pin Name Nonmaskable interrupt input pin Interrupt request input pins Interrupt request output pin Symbol I/O Function NMI Input Input of nonmaskable interrupt request ...
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Register Descriptions The INTC has the following registers. These registers are used to set the interrupt priorities and control detection of the external interrupt input signal. Table 6.2 Register Configuration Register Name Interrupt control register 0 Interrupt control register ...
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Interrupt Priority Registers 01, 02 (IPR01, IPR02, IPR05 to IPR15) IPR01, IPR02, and IPR05 to IPR15 are 16-bit readable/writable registers in which priority levels from are set for IRQ interrupts, PINT interrupts, and ...
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Register Name Bits Interrupt priority MTU5S register 13 (TGI5U, TGI5V, TGI5W) Interrupt priority SCIF0 register 14 Interrupt priority WAVEIF register 15 As shown in table 6.3, by setting the 4-bit groups (bits 15 to 12, bits 11 ...
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Interrupt Control Register 0 (ICR0) ICR0 is a 16-bit register that sets the input signal detection mode for the external interrupt input pin NMI, and indicates the input level at the NMI pin. ICR0 is initialized by a power-on ...
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Interrupt Control Register 1 (ICR1) ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ7 to IRQ0 individually: low level, falling edge, rising edge, or both edges. ICR1 is initialized by a power-on ...
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IRQ Interrupt Request Register (IRQRR) IRQRR is a 16-bit register that indicates interrupt requests from external input pins IRQ7 to IRQ0. If edge detection is set for the IRQ7 to IRQ0 interrupts, writing 0 to the IRQ7F to IRQ0F ...
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Initial Value Bit Bit Name 7 IRQ7F 0 6 IRQ6F 0 5 IRQ5F 0 4 IRQ4F 0 3 IRQ3F 0 2 IRQ2F 0 1 IRQ1F 0 0 IRQ0F 0 [Legend Note: * Only 0 can ...
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Bank Control Register (IBCR) IBCR is a 16-bit register that enables or disables use of register banks for each interrupt priority level. IBCR is initialized to H'0000 by a power-on reset. Bit E15 E14 E13 ...
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Bank Number Register (IBNR) IBNR is a 16-bit register that enables or disables use of register banks and register bank overflow exception. IBNR also indicates the bank number to which saving is performed next through the bits BN3 to ...
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Initial Value Bit Bit Name BN[3:0] 0000 R/W Description R Bank Number These bits indicate the bank number to which saving is performed next. When an interrupt using register banks is accepted, saving is performed to the ...
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Interrupt Sources There are five types of interrupt sources: NMI, user break, H-UDI, IRQ, and on-chip peripheral modules. Each interrupt has a priority level (0 to 16), with 0 the lowest and 16 the highest. When set to level ...
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IRQ Interrupts IRQ interrupts are input from pins IRQ7 to IRQ0. For the IRQ interrupts, low-level, falling-edge, rising-edge, or both-edge detection can be selected individually for each pin by the IRQ sense select bits (IRQ71S to IRQ01S and IRQ70S ...
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On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are generated by the following on-chip peripheral modules: • A/D converter (ADC) • Direct memory access controller (DMAC) • Compare match timer (CMT) • Bus state controller (BSC) • Watchdog timer ...
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Interrupt Exception Handling Vector Table and Priority Table 6.4 lists interrupt sources and their vector numbers, vector table address offsets, and interrupt priorities. Each interrupt source is allocated a different vector number and vector table address offset. Vector table ...
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Table 6.4 Interrupt Exception Handling Vectors and Priorities Interrupt Source Number Vector NMI 11 UBC 12 H-UDI 14 IRQ IRQ0 64 IRQ1 65 IRQ2 66 IRQ3 67 IRQ4 68 IRQ5 69 IRQ6 70 IRQ7 71 ADC ADI 92 Rev. 3.00 ...
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Interrupt Source Number Vector DMAC DMAC0 DEI0 108 HEI0 109 DMAC1 DEI1 112 HEI1 113 DMAC2 DEI2 116 HEI2 117 DMAC3 DEI3 120 HEI3 121 DMAC4 DEI4 124 HEI4 125 DMAC5 DEI5 128 HEI5 129 DMAC6 DEI6 132 HEI6 133 ...
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Interrupt Source Number Vector CMT CMI0 140 CMI1 144 BSC CMI 148 WDT ITI 152 MTU2 MTU0 TGI0A 156 TGI0B 157 TGI0C 158 TGI0D 159 TCI0V 160 TGI0E 161 TGI0F 162 MTU1 TGI1A 164 TGI1B 165 TCI1V 168 TCI1U 169 ...
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Interrupt Source Number Vector MTU2 MTU2 TGI2A 172 TGI2B 173 TCI2V 176 TCI2U 177 MTU3 TGI3A 180 TGI3B 181 TGI3C 182 TGI3D 183 TCI3V 184 MTU4 TGI4A 188 TGI4B 189 TGI4C 190 TGI4D 191 TCI4V 192 MTU5 TGI5U 196 TGI5V ...
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Interrupt Source Number Vector POE2 OEI1 200 OEI2 201 MTU2S MTU3S TGI3A 204 TGI3B 205 TGI3C 206 TGI3D 207 TCI3V 208 MTU4S TGI4A 212 TGI4B 213 TGI4C 214 TGI4D 215 TCI4V 216 MTU5S TGI5U 220 TGI5V 221 TGI5W 222 POE2 ...
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Interrupt Source Number Vector IIC3 STPI 228 NAKI 229 RXI 230 TXI 231 TEI 232 SCIF SCIF0 BRI0 240 ERI0 241 RXI0 242 TXI0 243 SCIF1 BRI1 244 ERI1 245 RXI1 246 TXI1 247 SCIF2 BRI2 248 ERI2 249 RXI2 ...
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Interrupt Source Number Vector SCIF SCIF3 BRI3 252 ERI3 253 RXI3 254 TXI3 255 WAVEIF ERR 256 WRXI 257 WTXI 258 Rev. 3.00 Mar. 04, 2009 Page 124 of 1168 REJ09B0344-0300 Interrupt Vector Interrupt Priority Vector Table Address Offset (Initial ...
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Operation 6.6.1 Interrupt Operation Sequence The sequence of interrupt operations is described below. Figure 6.2 shows the operation flow. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest-priority ...
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Notes: The interrupt source flag should be cleared in the interrupt handler. After clearing the interrupt source flag, "time from occurrence of interrupt request until interrupt controller identifies priority, compares it with mask bits in SR, and sends interrupt request ...
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Program execution state No Interrupt? Yes No NMI? Yes User break? Yes IRQOUT = low Read exception handling vector table Save SR to stack Copy accept-interrupt level Save PC to stack Branch to interrupt exception service ...
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Stack after Interrupt Exception Handling Figure 6.3 shows the stack after interrupt exception handling. Address 4n – – Notes: 1. PC: Start address of the next instruction (return destination instruction) 2. Always make ...
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Interrupt Response Time Table 6.5 lists the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception handling starts and fetching of the first instruction in the exception service routine begins. ...
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Item NMI 5 Icyc + Interrupt No register Min. response time banking 2 Bcyc + 1 Pcyc + Icyc + Max. 2 Bcyc + 1 Pcyc + 2( ⎯ Register Min. banking ...
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Icyc + 3 Bcyc + 1 Pcyc IRQ Instruction (instruction replacing interrupt exception handling) First instruction in interrupt exception service routine [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) F: Instruction fetch. ...
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Icyc + 3 Bcyc + 1 Pcyc IRQ First instruction in interrupt exception service routine First instruction in multiple interrupt exception service routine [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) Figure ...
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Icyc + 3 Bcyc + 1 Pcyc IRQ RESBANK instruction F D Instruction (instruction replacing interrupt exception handling) First instruction in interrupt exception service routine [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC ...
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Icyc + 3 Bcyc + 1 Pcyc IRQ F RESBANK instruction Instruction (instruction replacing interrupt exception handling) First instruction in interrupt exception service routine [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) ...
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Register Banks This LSI has fifteen register banks used to perform register saving and restoration required in the interrupt processing at high speed. Figure 6.10 shows the register bank configuration. Registers General registers Control registers System registers Bank control ...
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Banked Register and Input/Output of Banks (1) Banked Register The contents of the general registers (R0 to R14), global base register (GBR), multiply and accumulate registers (MACH and MACL), and procedure register (PR), and the vector table address offset ...
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Figure 6.12 shows the timing for saving to a register bank. Saving to a register bank takes place between the start of interrupt exception handling and the start of fetching the first instruction in the interrupt exception service routine. 2 ...
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Save and Restore Operations after Saving to All Banks If an interrupt occurs and usage of the register banks is enabled for the interrupt accepted by the CPU in a state where saving has been performed to all register ...
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Register Bank Exception There are two register bank exceptions (register bank errors): register bank overflow and register bank underflow. (1) Register Bank Overflow This exception occurs if, after data has been saved to all of the register banks, an ...
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Data Transfer with Interrupt Request Signals Interrupt request signals can be used to activate the DMAC and transfer data. Interrupt sources that are designated to activate the DMAC are masked without being input to the INTC. The mask condition ...
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Handling Interrupt Request Signals as Sources for CPU Interrupt but Not DMAC Activating 1 Do not select DMAC activating sources or clear the DME bit to 0. If, DMAC activating sources are selected, clear the DE bit to 0 ...
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Section 7 User Break Controller (UBC) The user break controller (UBC) provides functions that simplify program debugging. These functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. Instruction ...
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Figure 7.1 shows a block diagram of the UBC. I bus Access control IAB MAB FAB [Legend] BBR: Break bus cycle register BAR: Break address register BAMR: Break address mask register BRCR: Break control register Rev. 3.00 Mar. 04, 2009 ...
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Input/Output Pin Table 7.1 shows the pin configuration of the UBC. Table 7.1 Pin Configuration Pin Name Symbol UBCTRG UBC trigger 7.3 Register Descriptions The UBC has the following registers. Table 7.2 Register Configuration Channel Register Name 0 Break ...
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Break Address Register_0 (BAR_0) BAR_0 is a 32-bit readable/writable register. BAR_0 specifies the address used as a break condition in channel 0. The control bits CD0_1 and CD0_0 in the break bus cycle register_0 (BBR_0) select one of the ...
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Break Address Mask Register_0 (BAMR_0) BAMR_0 is a 32-bit readable/writable register. BAMR_0 specifies bits masked in the break address bits specified by BAR_0. BAMR_0 is initialized to H'00000000 by a power-on reset, but retains its previous value by a ...
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Break Bus Cycle Register_0 (BBR_0) BBR_0 is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user break interrupts, (2) including or excluding of the data bus value, (3) bus master of the I bus, (4) C ...
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Initial Value Bit Bit Name 7, 6 CD0[1: ID0[1: RW0[1: SZ0[1:0] 00 [Legend] x: Don't care R/W Description R/W C Bus Cycle/I Bus Cycle Select 0 Select the C bus cycle ...
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Break Address Register_1 (BAR_1) BAR_1 is a 32-bit readable/writable register. BAR_1 specifies the address used as a break condition in channel 1. The control bits CD1_1 and CD1_0 in the break bus cycle register_1 (BBR_1) select one of the ...
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Break Address Mask Register_1 (BAMR_1) BAMR_1 is a 32-bit readable/writable register. BAMR_1 specifies bits masked in the break address bits specified by BAR_1. BAMR_1 is initialized to H'00000000 by a power-on reset, but retains its previous value by a ...
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Break Bus Cycle Register_1 (BBR_1) BBR_1 is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user break interrupts, (2) including or excluding of the data bus value, (3) bus master of the I bus, (4) C ...
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Initial Value Bit Bit Name 7, 6 CD1[1: ID1[1: RW1[1: SZ1[1:0] 00 [Legend] x: Don't care R/W Description R/W C Bus Cycle/I Bus Cycle Select 1 Select the C bus cycle ...
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Break Address Register_2 (BAR_2) BAR_2 is a 32-bit readable/writable register. BAR_2 specifies the address used as a break condition in channel 2. The control bits CD2_1 and CD2_0 in the break bus cycle register_2 (BBR_2) select one of the ...
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Break Address Mask Register_2 (BAMR_2) BAMR_2 is a 32-bit readable/writable register. BAMR_2 specifies bits masked in the break address bits specified by BAR_2. BAMR_2 is initialized to H'00000000 by a power-on reset, but retains its previous value by a ...
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Break Bus Cycle Register_2 (BBR_2) BBR_2 is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user break interrups, (2) including or excluding of the data bus value, (3) bus master of the I bus, (4) C ...
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Initial Value Bit Bit Name 7, 6 CD2[1: ID2[1: RW2[1: SZ2[1:0] 00 [Legend] x: Don't care R/W Description R/W C Bus Cycle/I Bus Cycle Select 2 Select the C bus cycle ...
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Break Address Register_3 (BAR_3) BAR_3 is a 32-bit readable/writable register. BAR_3 specifies the address used as a break condition in channel 3. The control bits CD3_1 and CD3_0 in the break bus cycle register_3 (BBR_3) select one of the ...
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Break Address Mask Register_3 (BAMR_3) BAMR_3 is a 32-bit readable/writable register. BAMR_3 specifies bits masked in the break address bits specified by BAR_3. BAMR_3 is initialized to H'00000000 by a power-on reset, but retains its previous value by a ...
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Break Bus Cycle Register_3 (BBR_3) BBR_3 is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user break interrupts, (2) including or excluding of the data bus value, (3) bus master of the I bus, (4) C ...
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Initial Value Bit Bit Name 7, 6 CD3[1: ID3[1: RW3[1: SZ3[1:0] 00 [Legend] x: Don't care R/W Description R/W C Bus Cycle/I Bus Cycle Select 3 Select the C bus cycle ...
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Break Control Register (BRCR) BRCR sets the following conditions: 1. Specifies whether user breaks are set before or after instruction execution. 2. Specifies the pulse width of the UBCTRG output when a break condition is satisfied. BRCR is a ...
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Initial Value Bit Bit Name 15 SCMFC0 0 14 SCMFC1 0 13 SCMFC2 0 12 SCMFC3 0 11 SCMFD0 0 R/W Description R/W C Bus Cycle Condition Match Flag 0 When the C bus cycle condition in the break conditions ...
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Initial Value Bit Bit Name 10 SCMFD1 0 9 SCMFD2 0 8 SCMFD3 0 7 PCB3 0 6 PCB2 0 Rev. 3.00 Mar. 04, 2009 Page 164 of 1168 REJ09B0344-0300 R/W Description R/W I Bus Cycle Condition Match Flag 1 ...
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Initial Value Bit Bit Name 5 PCB1 0 4 PCB0 0 ⎯ All 0 R/W Description R/W PC Break Select 1 Selects the break timing of the instruction fetch cycle for channel 1 as before or after ...
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Operation 7.4.1 Flow of the User Break Operation The flow from setting of break conditions to user break interrupt exception handling is described below: 1. The break address is set in a break address register (BAR). The masked address ...
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I bus cycles (including read fill cycles) resulting from instruction fetches on the C bus by the CPU are defined as instruction fetch cycles on the I bus, while other bus cycles are defined as data access cycles. ⎯ ...
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Break on Data Access Cycle 1. If the C bus is specified as a break condition for data access break, condition comparison is performed for the virtual address accessed by the executed instructions, and a break occurs if the ...
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Value of Saved Program Counter When a break occurs, the address of the instruction from where execution resumed is saved to the stack, and the exception handling state is entered. If the C bus (FAB)/instruction fetch ...
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Usage Examples (1) Break Condition Specified for C Bus Instruction Fetch Cycle (Example 1-1) • Register specifications BAR_0 = H'00000404, BAMR_0 = H'00000000, BBR_0 = H'0054, BAR_1 = H'00008010, BAMR_1 = H'00000006, BBR_1 = H'0054, BRCR = H'00000020 <Channel ...
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Register specifications BBR_0 = H'0054, BAR_0 = H'00008404, BAMR_0 = H'00000FFF, BBR_1 = H'0054, BAR_1 = H'00008010, BAMR_1 = H'00000006, BRCR = H'00000020 <Channel 0> Address: H'00008404, Address mask: H'00000FFF Bus cycle: C bus/instruction fetch (after instruction ...
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Break Condition Specified for I Bus Data Access Cycle (Example 3-1) • Register specifications BBR_0 = H'0094, BAR_0 = H'00314156, BAMR_0 = H'00000000, BBR_1 = H'12A9, BAR_1 = H'00055555, BAMR_1 = H'00000000, BRCR = H'00000000 <Channel 0> Address: H'00314156, ...
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Usage Notes 1. The CPU can read from or write to the UBC registers via the I bus. Accordingly, during the period from executing an instruction to rewrite the UBC register till the new value is actually rewritten, the ...
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