R0K572115S000BE Renesas Electronics America, R0K572115S000BE Datasheet - Page 323

• Manufacturer Part Number: R0K572115S000BE
• Description: KIT STARTER FOR SH7211
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: Microcontrollerr

Specifications of R0K572115S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7211
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

peripheral bus (the example in figure 8.41 is for 4 × Bφ). Therefore, when Bφ:Pφ is 4:1, data is
transferred from the I bus to the peripheral bus in time (1+m) × Bφ, where m = 0 to 3 periods.
Note that the relationship between the timing with which the data appears on the I bus and the Pφ
rising edge depends on the program execution state. In figure 8.41, since n = 0 and m = 3, the
access time will be 2 × Iφ + 4 × Bφ + 2 × Pφ.
Figure 8.42 shows an example of the write timing to the peripheral bus when the relationship
between the clocks is Iφ:Bφ:Pφ = 4:2:1. Although transfers from the C bus to the peripheral bus
are performed the same way for write, for read, the value read from the peripheral bus must be
transferred to the CPU. Although the transfers from the peripheral bus to the I bus and from the I
bus to the C bus are all performed on the corresponding bus clock rising edge, since Iφ ≥ Bφ ≥ Pφ,
(2 + 1) × Iφ periods are actually required. In the example in figure 8.42, since n = 1, m = 1, and i =
1, the access period will be 3 × Iφ + 2 × Bφ + 2 × Pφ + 3 × Iφ.
I φ
C bus
B φ
I bus
P φ
Peripheral bus
I φ
C bus
B φ
I bus
P φ
Peripheral bus
Figure 8.41 Internal Peripheral I/O Register Timing when Iφ:Bφ:Pφ = 4:4:1
Figure 8.42 Internal Peripheral I/O Register Timing when Iφ:Bφ:Pφ = 4:2:1
(2+n) × I φ
(2+n) × I φ
(1+m) × B φ
(1+m) × B φ
2 × P φ
Rev. 3.00 Mar. 04, 2009 Page 297 of 1168
2 × P φ
REJ09B0344-0300
(2+I) × I φ