R0K572115S000BE Renesas Electronics America, R0K572115S000BE Datasheet - Page 192

• Manufacturer Part Number: R0K572115S000BE
• Description: KIT STARTER FOR SH7211
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: Microcontrollerr

Specifications of R0K572115S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7211
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

7.4
7.4.1
The flow from setting of break conditions to user break interrupt exception handling is described
below:
1. The break address is set in a break address register (BAR). The masked address bits are set in a
2. In the case where the break conditions are satisfied, the UBC sends a user break interrupt
3. On receiving a user break interrupt request signal, the INTC determines its priority. Since the
4. Condition match flags (SCMFC and SCMFD) can be used to check which condition has been
5. It is possible that the breaks set in channels 0 to 3 occur around the same time. In this case,
6. When selecting the I bus as the break condition, note as follows:
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REJ09B0344-0300
break address mask register (BAMR). The bus break conditions are set in the break bus cycle
register (BBR). Three control bit groups of BBR (C bus cycle/I bus cycle select, instruction
fetch/data access select, and read/write select) are each set. No user break will be generated if
even one of these groups is set to 00. The relevant break control conditions are set in the bits of
the break control register (BRCR). Make sure to set all registers related to breaks before setting
BBR, and branch after reading from the last written register. The newly written register values
become valid from the instruction at the branch destination.
request to the CPU, sets the C bus condition match flag (SCMFC) or I bus condition match
flag (SCMFD) for the appropriate channel, and outputs a pulse to the UBCTRG pin with the
width set by the CKS1 and CKS0 bits. Setting the UBID bit in BBR to 1 enables external
monitoring of the trigger output without requesting user break interrupts.
user break interrupt has a priority level of 15, it is accepted when the priority level set in the
interrupt mask level bits (I3 to I0) of the status register (SR) is 14 or lower. If the I3 to I0 bits
are set to a priority level of 15, the user break interrupt is not accepted, but the conditions are
checked, and condition match flags are set if the conditions match. For details on ascertaining
the priority, see section 6, Interrupt Controller (INTC).
satisfied. They are set when the conditions match, but are not reset. To use these flags again,
write 0 to the corresponding bit of the flags.
there will be only one user break request to the CPU, but these four break channel match flags
may be set at the same time.
⎯ Several bus masters, including the CPU and DMAC, are connected to the I bus. The UBC
monitors bus cycles generated by the bus master specified by BBR, and determines the
condition match.
Operation
Flow of the User Break Operation