R0K572115S000BE Renesas Electronics America, R0K572115S000BE Datasheet - Page 248

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R0K572115S000BE

Manufacturer Part Number
R0K572115S000BE
Description
KIT STARTER FOR SH7211
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
Microcontrollerr
Datasheets

Specifications of R0K572115S000BE

Contents
CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
For Use With/related Products
SH7211
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Rev. 3.00 Mar. 04, 2009 Page 222 of 1168
REJ09B0344-0300
Bit
15, 14
13
12
11
DEEP
Bit Name
SLOW
RFSH
Initial
Value
All 0
0
0
0
R/W
R
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Deep Power-Down Mode
This bit is valid for low-power SDRAM. If the RFSH or
RMODE bit is set to 1 while this bit is set to 1, the deep
power-down entry command is issued and the low-
power SDRAM enters deep power-down mode.
0: Self-refresh mode
1: Deep power-down mode
Low-Frequency Mode
Specifies the output timing of command, address, and
write data for SDRAM and the latch timing of read data
from SDRAM. Setting this bit makes the hold time for
command, address, write and read data extended for
half cycle (output or read at the falling edge of CK).
This mode is suitable for SDRAM with low-frequency
clock.
0: Command, address, and write data for SDRAM is
1: Command, address, and write data for SDRAM is
Refresh Control
Specifies whether or not the refresh operation of the
SDRAM is performed.
0: No refresh
1: Refresh
output at the rising edge of CK. Read data from
SDRAM is latched at the rising edge of CK.
output at the falling edge of CK. Read data from
SDRAM is latched at the falling edge of CK.

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