R0K572115S000BE Renesas Electronics America, R0K572115S000BE Datasheet - Page 93

• Manufacturer Part Number: R0K572115S000BE
• Description: KIT STARTER FOR SH7211
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: Microcontrollerr

Specifications of R0K572115S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7211
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 4.3
Notes:
Caution:
Clock
Operating
Mode
6
FRQCR
Setting
H'1000
H'1001
H'1003
H'1005
H'1101
H'1103
H'1105
H'1111
H'1113
H'1115
H'1303
H'1305
H'1313
H'1315
H'1333
H'1335
1. The ratio of clock frequencies, where the input clock frequency is assumed to be 1.
2. The frequency of the clock input from the EXTAL pin or the frequency of the crystal resonator.
1. The frequency of the internal clock (Iφ) is the frequency of the signal input to the CK pin after
2. The frequency of the peripheral clock (Pφ) is the frequency of the signal input to the CK pin after
3. The frequency multiplier of PLL circuit 1 can be selected as ×1, ×2, or ×4. The divisor of the
4. The signal output by PLL circuit 1 is the signal on the CK pin multiplied by the frequency
Relationship between Clock Operating Mode and Frequency Range
multiplication by the frequency-multiplier of PLL circuit 1 and division by the divider's divisor. Set
the frequency of the internal clock to 160 MHz or less but not less than the frequency of the
signal on the CK pin.
multiplication by the frequency-multiplier of PLL circuit 1 and division by the divider's divisor. Set
the frequency of the peripheral clock to 40 MHz or less. In addition, do not set a higher
frequency for the internal clock than the frequency on the CK pin.
divider can be selected as ×1, ×1/2, ×1/4, or ×1/8. The settings are made in the frequency-
control register (FRQCR).
multiplier of PLL circuit 1. Ensure that the frequency of the signal from PLL circuit 1 is no more
than 160 MHz.
PLL
Circuit 1
On (× 1)
On (× 1)
On (× 1)
On (× 1)
On (× 2)
On (× 2)
On (× 2)
On (× 2)
On (× 2)
On (× 2)
On (× 4)
On (× 4)
On (× 4)
On (× 4)
On (× 4)
On (× 4)
PLL Frequency
Multiplier
PLL
Circuit 2
On (×4)
On (×4)
On (×4)
On (×4)
On (×4)
On (×4)
On (×4)
On (×4)
On (×4)
On (×4)
On (×4)
On (×4)
On (×4)
On (×4)
On (×4)
On (×4)
Ratio of
Internal Clock
Frequencies
(I:B:P)*
4:4:4
4:4:2
4:4:1
4:4:1/2
8:4:4
8:4:2
8:4:1
4:4:4
4:4:2
4:4:1
16:4:4
16:4:2
8:4:4
8:4:2
4:4:4
4:4:2
1
Input Clock*
8 to 10
8 to 10
8 to 10
8 to 10
8 to 10
8 to 10
8 to 10
8 to 10
8 to 10
8 to 10
8 to 10
8 to 10
8 to 10
8 to 10
8 to 10
8 to 10
2
Output Clock
(CK Pin)
32 to 40
32 to 40
32 to 40
32 to 40
32 to 40
32 to 40
32 to 40
32 to 40
32 to 40
32 to 40
32 to 40
32 to 40
32 to 40
32 to 40
32 to 40
32 to 40
Selectable Frequency Range (MHz)
Rev. 3.00 Mar. 04, 2009 Page 67 of 1168
Internal Clock
(Iφ)
32 to 40
32 to 40
32 to 40
32 to 40
64 to 80
64 to 80
64 to 80
32 to 40
32 to 40
32 to 40
128 to 160
128 to 160
64 to 80
64 to 80
32 to 40
32 to 40
Bus Clock
(Bφ)
32 to 40
32 to 40
32 to 40
32 to 40
32 to 40
32 to 40
32 to 40
32 to 40
32 to 40
32 to 40
32 to 40
32 to 40
32 to 40
32 to 40
32 to 40
32 to 40
REJ09B0344-0300
Peripheral
Clock (Pφ)
32 to 40
16 to 20
8 to 10
4 to 5
32 to 40
16 to 20
8 to 10
32 to 40
16 to 20
8 to 10
32 to 40
16 to 20
32 to 40
16 to 20
32 to 40
16 to 20