R0K572115S000BE Renesas Electronics America, R0K572115S000BE Datasheet - Page 196

• Manufacturer Part Number: R0K572115S000BE
• Description: KIT STARTER FOR SH7211
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: Microcontrollerr

Specifications of R0K572115S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7211
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

7.4.5
(1)
(Example 1-1)
• Register specifications
(Example 1-2)
• Register specifications
Rev. 3.00 Mar. 04, 2009 Page 170 of 1168
REJ09B0344-0300
BAR_0 = H'00000404, BAMR_0 = H'00000000, BBR_0 = H'0054, BAR_1 = H'00008010,
BAMR_1 = H'00000006, BBR_1 = H'0054, BRCR = H'00000020
<Channel 0>
Address:
Bus cycle: C bus/instruction fetch (after instruction execution)/read (operand size is not
<Channel 1>
Address:
Bus cycle: C bus/instruction fetch (before instruction execution)/read (operand size is not
A user break occurs after an instruction of address H'00000404 is executed or before
instructions of addresses H'00008010 to H'00008016 are executed.
BAR_0 = H'00027128, BAMR_0 = H'00000000, BBR_0 = H'005A, BAR_1= H'00031415,
BAMR_1 = H'00000000, BBR_1 = H'0054, BRCR = H'00000000
<Channel 0>
Address:
Bus cycle: C bus/instruction fetch (before instruction execution)/write/word
<Channel 1>
Address:
Bus cycle: C bus/instruction fetch (before instruction execution)/read (operand size is not
On channel 0, a user break does not occur since instruction fetch is not a write cycle. On
channel 1, a user break does not occur since instruction fetch is performed for an even address.
Break Condition Specified for C Bus Instruction Fetch Cycle
Usage Examples
included in the condition)
included in the condition)
included in the condition)
H'00000404, Address mask: H'00000000
H'00008010, Address mask: H'00000006
H'00027128, Address mask: H'00000000
H'00031415, Address mask: H'00000000