R0K572115S000BE Renesas Electronics America, R0K572115S000BE Datasheet - Page 255

• Manufacturer Part Number: R0K572115S000BE
• Description: KIT STARTER FOR SH7211
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: Microcontrollerr

Specifications of R0K572115S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7211
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8.5
8.5.1
This LSI supports big endian in which the 0 address is the most significant byte (MSB), and little
endian in which the 0 address is the least significant byte (LSB) in the byte data. In a space of
areas 1 to 7, endian can be set by the CSnBCR setting while the target space is not accessed. In a
space of area 0, the CSnBCR setting is invalid in on-chip ROM-disabled mode. In on-chip ROM-
enabled mode, endian can be set by the CSnBCR setting in a space of areas 0 to 7.
Two data bus widths (8 bits and 16 bits) are available for normal memory and SRAM with byte
selection. Only 16-bit data bus width is available for SDRAM. For MPX-I/O, the data bus width is
fixed at 8 bits or 16 bits, or 8 bits or 16 bits can be selected by the access address. Data alignment
is performed in accordance with the data bus width of the device. This also means that when
longword data is read from a byte-width device, the read operation must be done four times. In
this LSI, data alignment and conversion of data length is performed automatically between the
respective interfaces.
Tables 8.5 to 8.8 show the relationship between device data width and access unit. Note that
addresses corresponding to the strobe signals for the 16-bit bus width differ between big endian
and little endian. WE1 indicates the 0 address in big-endian mode, but WE0 indicates the 0
address in little-endian mode.
Table 8.5
Operation
Byte access at 0
Byte access at 1
Byte access at 2
Byte access at 3
Word access at 0
Word access at 2
Longword
access at 0
Operation
Endian/Access Size and Data Alignment
16-Bit External Device Access and Data Alignment in Big-Endian Mode
1st time at 0
2nd time at 2
D15 to D8
Data 7 to 0
⎯
Data 7 to 0
⎯
Data 15 to 8
Data 15 to 8
Data 23 to 16
Data 7 to 0
Data Bus
D7 to D0
⎯
Data 7 to 0
⎯
Data 7 to 0
Data 7 to 0
Data 7 to 0
Data 31 to 24
Data 15 to 8
Rev. 3.00 Mar. 04, 2009 Page 229 of 1168
WE1, DQMLU
Assert
⎯
Assert
⎯
Assert
Assert
Assert
Assert
Strobe Signals
REJ09B0344-0300
WE0, DQMLL
⎯
Assert
⎯
Assert
Assert
Assert
Assert
Assert