R0K572115S000BE Renesas Electronics America, R0K572115S000BE Datasheet - Page 162

• Manufacturer Part Number: R0K572115S000BE
• Description: KIT STARTER FOR SH7211
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: Microcontrollerr

Specifications of R0K572115S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7211
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.8.1
(1)
The contents of the general registers (R0 to R14), global base register (GBR), multiply and
accumulate registers (MACH and MACL), and procedure register (PR), and the vector table
address offset are banked.
(2)
This LSI has fifteen register banks, bank 0 to bank 14. Register banks are stacked in first-in last-
out (FILO) sequence. Saving takes place in order, beginning from bank 0, and restoration takes
place in the reverse order, beginning from the last bank saved to.
6.8.2
(1)
Figure 6.11 shows register bank save operations. The following operations are performed when an
interrupt for which usage of register banks is allowed is accepted by the CPU:
a. Assume that the bank number bit value in the bank number register (IBNR), BN, is i before the
b. The contents of registers R0 to R14, GBR, MACH, MACL, and PR, and the interrupt vector
c. The BN value is incremented by 1.
Rev. 3.00 Mar. 04, 2009 Page 136 of 1168
REJ09B0344-0300
interrupt is generated.
table address offset (VTO) of the accepted interrupt are saved in the bank indicated by BN,
bank i.
Banked Register
Register Banks
Saving to Bank
Banked Register and Input/Output of Banks
Bank Save and Restore Operations
(c)
BN
+1
Figure 6.11 Bank Save Operations
(a)
Register banks
Bank i + 1
Bank 14
Bank 0
Bank 1
Bank i
:
:
:
:
(b)
R0 to R14
Registers
MACH
MACL
GBR
VTO
PR