R0K572115S000BE Renesas Electronics America, R0K572115S000BE Datasheet - Page 23

• Manufacturer Part Number: R0K572115S000BE
• Description: KIT STARTER FOR SH7211
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: Microcontrollerr

Specifications of R0K572115S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7211
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

20.2 Port B ................................................................................................................................. 870
20.3 Port D................................................................................................................................. 877
20.4 Port F.................................................................................................................................. 881
20.5 Usage Note......................................................................................................................... 883
Section 21 Flash Memory ....................................................................................885
21.1 Features.............................................................................................................................. 885
21.2 Overview............................................................................................................................ 887
21.3 Input/Output Pins ............................................................................................................... 895
21.4 Register Descriptions ......................................................................................................... 895
21.5 On-Board Programming Mode .......................................................................................... 920
21.6 Protection ........................................................................................................................... 940
21.7 Usage Notes ....................................................................................................................... 943
20.1.3 Port A Port Registers H, L (PAPRH, PAPRL) ..................................................... 868
20.2.1 Register Descriptions ............................................................................................ 871
20.2.2 Port B Data Registers H, L (PBDRH, PBDRL).................................................... 871
20.2.3 Port B Port Registers H, L (PBPRH, PBPRL) ...................................................... 875
20.3.1 Register Descriptions ............................................................................................ 877
20.3.2 Port D Data Register L (PDDRL) ......................................................................... 878
20.3.3 Port D Port Register L (PDPRL)........................................................................... 880
20.4.1 Register Descriptions ............................................................................................ 881
20.4.2 Port F Data Register (PFDR) ................................................................................ 882
21.2.1 Block Diagram...................................................................................................... 887
21.2.2 Operating Mode .................................................................................................... 888
21.2.3 Mode Comparison................................................................................................. 890
21.2.4 Flash Memory Configuration................................................................................ 891
21.2.5 Block Division ...................................................................................................... 892
21.2.6 Programming/Erasing Interface ............................................................................ 893
21.4.1 Registers ............................................................................................................... 895
21.4.2 Programming/Erasing Interface Registers ............................................................ 898
21.4.3 Programming/Erasing Interface Parameters ......................................................... 905
21.5.1 Boot Mode ............................................................................................................ 920
21.5.2 User Program Mode.............................................................................................. 924
21.5.3 User Boot Mode.................................................................................................... 935
21.6.1 Hardware Protection ............................................................................................. 940
21.6.2 Software Protection............................................................................................... 941
21.6.3 Error Protection..................................................................................................... 941
21.7.1 Switching between User MAT and User Boot MAT............................................ 943
21.7.2 Interrupts during Programming/Erasing ............................................................... 944
21.7.3 Other Notes ........................................................................................................... 946
Rev. 3.00 Mar. 04, 2009 Page xxi of xxiv
REJ09B0344-0300