R0K572115S000BE Renesas Electronics America, R0K572115S000BE Datasheet - Page 353

• Manufacturer Part Number: R0K572115S000BE
• Description: KIT STARTER FOR SH7211
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: Microcontrollerr

Specifications of R0K572115S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7211
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

9.4
When there is a DMA transfer request, the DMAC starts the transfer according to the
predetermined channel priority order; when the transfer end conditions are satisfied, it ends the
transfer. Transfers can be requested in three modes: auto request, external request, and on-chip
peripheral module request. In bus mode, burst mode or cycle steal mode can be selected.
9.4.1
After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA
transfer count registers (DMATCR), DMA channel control registers (CHCR), DMA operation
register (DMAOR), and DMA extension resource selector (DMARS) are set for the target transfer
conditions, the DMAC transfers data according to the following procedure:
1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0)
2. When a transfer request comes and transfer is enabled, the DMAC transfers one transfer unit of
3. When half of the specified transfer count is exceeded (when DMATCR reaches half of the
4. When transfer has been completed for the specified count (when DMATCR reaches 0), the
5. When an address error in the DMAC or an NMI interrupt is generated, the transfer is
Figure 9.2 is a flowchart of this procedure.
data (depending on the TS0 and TS1 settings). For an auto request, the transfer begins
automatically when the DE bit and DME bit are set to 1. The DMATCR value will be
decremented by 1 for each transfer. The actual transfer flows vary by address mode and bus
mode.
initial value), an HEI interrupt is sent to the CPU if the HIE bit in CHCR is set to 1.
transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt is sent to
the CPU.
terminated. Transfers are also terminated when the DE bit in CHCR or the DME bit in
DMAOR is cleared to 0.
Operation
Transfer Flow
Rev. 3.00 Mar. 04, 2009 Page 327 of 1168
REJ09B0344-0300