R0K572115S000BE Renesas Electronics America, R0K572115S000BE Datasheet - Page 955

• Manufacturer Part Number: R0K572115S000BE
• Description: KIT STARTER FOR SH7211
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: Microcontrollerr

Specifications of R0K572115S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7211
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

(2.6) The operating frequency is set to the FPEFEQ parameter and the user branch destination is
(2.7) Initialization
MOV.L #DLTOP+32,R1
JSR
NOP
set to the FUBRA parameter for initialization.
1. The current frequency of the CPU clock is set to the FPEFEQ parameter (general register
2. The start address in the user branch destination is set to the (FUBRA: CPU general register
When a programming program is downloaded, the initialization program is also downloaded to
on-chip RAM. There is an entry point of the initialization program in the area from (download
start address set by FTDAR) + 32 bytes. The subroutine is called and initialization is executed
by using the following steps.
1. The general registers other than R0 are saved in the initialization program.
2. R0 is a return value of the FPFR parameter.
3. Since the stack area is used in the initialization program, a stack area of 256 bytes or more
4. Interrupts can be accepted during the execution of the initialization program. However, the
R4). The settable range Iφ of the FPEFEQ parameter is 32 to 40
When the frequency is set out of this range, an error is returned to the FPFR parameter of
the initialization program and initialization is not performed. For details on the frequency
setting, see the description in section 21.4.3 (2.1), Flash Programming/Erasing Frequency
Parameter (FPEFEQ: General Register R4 of CPU).
R5) parameter.
When the user branch processing is not required, 0 must be set to FUBRA.
When the user branch is executed, the branch destination is executed in flash memory other
than the one that is to be programmed. The area of the on-chip program that is downloaded
cannot be set.
The program processing must be returned from the user branch processing by the RTS
instruction.
See the description in section 21.4.3 (2.2), Flash User Branch Address Setting Parameter
(FUBRA: General Register R5 of CPU).
must be reserved in RAM.
program storage area and stack area in on-chip RAM and register values must not be
destroyed.
@R1
; Set entry address to R1
; Call initialization routine
Rev. 3.00 Mar. 04, 2009 Page 929 of 1168
MHz.
REJ09B0344-0300