R0K572115S000BE Renesas Electronics America, R0K572115S000BE Datasheet - Page 506

• Manufacturer Part Number: R0K572115S000BE
• Description: KIT STARTER FOR SH7211
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: Microcontrollerr

Specifications of R0K572115S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7211
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

(c)
In complementary PWM mode, there are six registers that must be initialized. In addition, there is
a register that specifies whether to generate dead time (it should be used only when dead time
generation should be disabled).
Before setting complementary PWM mode with bits MD3 to MD0 in the timer mode register
(TMDR), the following initial register values must be set.
TGRC_3 operates as the buffer register for TGRA_3, and should be set with 1/2 the PWM carrier
cycle + dead time Td. The timer cycle buffer register (TCBR) operates as the buffer register for
the timer cycle data register (TCDR), and should be set with 1/2 the PWM carrier cycle. Set dead
time Td in the timer dead time data register (TDDR).
When dead time is not needed, the TDER bit in the timer dead time enable register (TDER) should
be cleared to 0, TGRC_3 and TGRA_3 should be set to 1/2 the PWM carrier cycle + 1, and TDDR
should be set to 1.
Set the respective initial PWM duty values in buffer registers TGRD_3, TGRC_4, and TGRD_4.
The values set in the five buffer registers excluding TDDR are transferred simultaneously to the
corresponding compare registers when complementary PWM mode is set.
Set TCNT_4 to H'0000 before setting complementary PWM mode.
Table 10.56 Registers and Counters Requiring Initialization
Note: The TGRC_3 set value must be the sum of 1/2 the PWM carrier cycle set in TCBR and
Rev. 3.00 Mar. 04, 2009 Page 480 of 1168
REJ09B0344-0300
Register/Counter
TGRC_3
TDDR
TCBR
TGRD_3, TGRC_4, TGRD_4
TCNT_4
Initialization
dead time Td set in TDDR. When dead time generation is disabled by TDER, TGRC_3
must be set to 1/2 the PWM carrier cycle + 1.
Set Value
1/2 PWM carrier cycle + dead time Td
(1/2 PWM carrier cycle + 1 when dead time generation
is disabled by TDER)
Dead time Td (1 when dead time generation is
disabled by TDER)
1/2 PWM carrier cycle
Initial PWM duty value for each phase
H'0000