R0K572115S000BE Renesas Electronics America, R0K572115S000BE Datasheet - Page 392

• Manufacturer Part Number: R0K572115S000BE
• Description: KIT STARTER FOR SH7211
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: Microcontrollerr

Specifications of R0K572115S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7211
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 10.10 TPSC1 and TPSC0 (Channel 5)
Note: Bits 7 to 2 are reserved in channel 5. These bits are always read as 0. The write value
10.3.2
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of
each channel. The MTU2 has five TMDR registers, one each for channels 0 to 4. TMDR register
settings should be changed only when TCNT operation is stopped.
Rev. 3.00 Mar. 04, 2009 Page 366 of 1168
REJ09B0344-0300
Channel
5
Bit
7
6
should always be 0.
Bit Name
—
BFE
Timer Mode Register (TMDR)
Bit 1
TPSC1
0
1
Initial value:
Initial
Value
0
0
Bit 0
TPSC0
0
1
0
1
R/W:
Bit:
R
7
0
-
R/W
R
R/W
Description
Internal clock: counts on Pφ/1
Internal clock: counts on Pφ/4
Internal clock: counts on Pφ/16
Internal clock: counts on Pφ/64
R/W
BFE
6
0
Description
This bit is always read as 0. The write value should
always be 0.
Specifies whether TGRE_0 and TGRF_0 are to operate
in the normal way or to be used together for buffer
operation.
TGRF compare match is generated when TGRF is
used as the buffer register.
In channels 1 to 4, this bit is reserved. It is always read
as 0 and the write value should always be 0.
0: TGRE_0 and TGRF_0 operate normally
1: TGRE_0 and TGRF_0 used together for buffer
Reserved
Buffer Operation E
R/W
BFB
5
0
operation
R/W
BFA
4
0
R/W
3
0
R/W
2
0
MD[3:0]
R/W
1
0
R/W
0
0