R0K572115S000BE Renesas Electronics America, R0K572115S000BE Datasheet - Page 325

• Manufacturer Part Number: R0K572115S000BE
• Description: KIT STARTER FOR SH7211
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: Microcontrollerr

Specifications of R0K572115S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7211
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The DMAC can be used in place of the CPU to perform high-speed transfers between external
devices that have DACK (transfer request acknowledge signal), external memory, on-chip
memory, memory-mapped external devices, and on-chip peripheral modules.
9.1
• Number of channels: Eight channels (channels 0 to 7) selectable
• 4-Gbyte physical address space
• Transfer data length is selectable: Byte, word (two bytes), longword (four bytes), and 16 bytes
• Maximum transfer count: 16,777,216 transfers (24 bits)
• Address mode: Dual address mode and single address mode are supported.
• Transfer requests
• Selectable bus modes
• Selectable channel priority levels: The channel priority levels are selectable between fixed
• Interrupt request: An interrupt request can be sent to the CPU on completion of half- or full-
• External request detection: There are following four types of DREQ input detection.
Four channels (channels 0 to 3) can receive external requests.
(longword × 4)
⎯ External request
⎯ On-chip peripheral module request
⎯ Auto request
The following modules can issue on-chip peripheral module requests.
⎯ Eight SCIF sources, two IIC3 sources, one A/D converter source, five MTU2 sources, and
⎯ Cycle steal mode (normal mode and intermittent mode)
⎯ Burst mode
mode and round-robin mode.
data transfer. Through the HE and HIE bits in CHCR, an interrupt is specified to be issued to
the CPU when half of the initially specified DMA transfer is completed.
⎯ Low level detection
⎯ High level detection
⎯ Rising edge detection
⎯ Falling edge detection
Section 9 Direct Memory Access Controller (DMAC)
two CMT sources
Features
Rev. 3.00 Mar. 04, 2009 Page 299 of 1168
REJ09B0344-0300