R0K572115S000BE Renesas Electronics America, R0K572115S000BE Datasheet - Page 178

• Manufacturer Part Number: R0K572115S000BE
• Description: KIT STARTER FOR SH7211
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: Microcontrollerr

Specifications of R0K572115S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7211
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

7.3.6
BBR_1 is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user
break interrupts, (2) including or excluding of the data bus value, (3) bus master of the I bus, (4) C
bus cycle or I bus cycle, (5) instruction fetch or data access, (6) read or write, and (7) operand size
as the break conditions of channel 1. BBR_1 is initialized to H'0000 by a power-on reset, but
retains its previous value by a manual reset or in software standby mode or sleep mode.
Initial value:
Rev. 3.00 Mar. 04, 2009 Page 152 of 1168
REJ09B0344-0300
Bit
15, 14
13
12 to 10 ⎯
9, 8
R/W:
Bit:
Break Bus Cycle Register_1 (BBR_1)
Bit Name
⎯
UBID1
CP1[1:0]
15
R
0
-
14
R
0
-
UBID1
R/W
13
0
Initial
Value
All 0
0
All 0
00
12
R
0
-
11
R
0
-
R/W
R
R/W
R
R/W
10
R
0
-
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
User Break Interrupt Disable 1
Disables or enables user break interrupt requests
when a channel-1 break condition is satisfied.
0: User break interrupt requests enabled
1: User break interrupt requests disabled
Reserved
These bits are always read as 0. The write value
should always be 0.
I-Bus Bus Master Select 1
Select the bus master when the bus cycle of the
channel-1 break condition is the I bus cycle. However,
when the C bus cycle is selected, this bit is invalidated
(only the CPU cycle).
x1: CPU cycle is included in break conditions
1x: DMAC cycle is included in break conditions
R/W
9
0
CP1[1:0]
R/W
8
0
R/W
7
0
CD1[1:0]
R/W
6
0
R/W
5
0
ID1[1:0]
R/W
4
0
R/W
3
0
RW1[1:0]
R/W
2
0
R/W
1
0
SZ1[1:0]
R/W
0
0