R0K572115S000BE Renesas Electronics America, R0K572115S000BE Datasheet - Page 793

• Manufacturer Part Number: R0K572115S000BE
• Description: KIT STARTER FOR SH7211
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: Microcontrollerr

Specifications of R0K572115S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7211
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

16.7
16.7.1
With multi-master used, if the transfer rate setting (CKS[3:0] in ICCR1) of I
slower than the other masters, the SCL with unexpected width may be output in rare cases.
To prevent this problem, the transfer rate of I
1/1.8 of the highest transfer rate among the other masters.
16.7.2
If ICDRR is read near the falling edge of 8th clock, the receive data will not be received in some
cases. In addition, if RCVD is set to 1 near the falling edge of 8th clock, a stop condition cannot
be issued in some cases. To prevent these errors, one of the following two methods should be
selected.
1. In master receive mode, ICDRR should be read before the falling edge of 8th clock.
2. In master receive mode, RCVD should be set to 1 and the processing should be performed in
16.7.3
In master receive mode operation, ACKBT should be set before the 8th falling edge of SCL in the
final data transfer during continuous data transfer. Otherwise, the slave device may overrun.
16.7.4
If the master transmission is set according to the MST and TRS bit settings while multiple masters
are used, the conflicting status in which the AL bit in ICSR is set to 1 in master transmit mode
(MST and TRS are set to 1) depending on the arbitration lost generation timing during TRS bit
handling instruction execution.
This problem can be avoided by the following methods.
• When multiple masters are used, the MST and TRS bits should be set by a MOV instruction.
• When an arbitration lost occurs, check if both MST and TRS bits are cleared to 0. If either or
byte units.
both of MST and TRS bits are not cleared to 0, both the bits should be cleared to 0.
Usage Notes
Note on Multiple Master Usage
Note on Master Receive Mode
Note on Master Receive Mode with ACKBT Setting
Note on MST and TRS Bit Status When an Arbitration was Lost
2
C should be specified as equal to or higher than
Rev. 3.00 Mar. 04, 2009 Page 767 of 1168
Section 16 I
2
C in this LSI is
2
C Bus Interface 3 (IIC3)
REJ09B0344-0300