R0K572115S000BE Renesas Electronics America, R0K572115S000BE Datasheet - Page 99

• Manufacturer Part Number: R0K572115S000BE
• Description: KIT STARTER FOR SH7211
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: Microcontrollerr

Specifications of R0K572115S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7211
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.5
The frequency of the internal clock (Iφ) and peripheral clock (Pφ) can be changed either by
changing the multiplication rate of PLL circuit 1 or by changing the division rates of divider. All
of these are controlled by software through the frequency control register (FRQCR). The methods
are described below.
4.5.1
A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed. When the
multiplication rate is changed, the LSI temporarily stops automatically and the internal watchdog
timer (WDT) starts counting the settling time. When the count of the WDT overflows, the LSI
restarts operating with the set clock frequency. The following shows this setting procedure.
1. In the initial state, the multiplication rate of PLL circuit 1 is 1 time.
2. Set a value that will become the specified oscillation settling time in the WDT and stop the
3. Set the desired value in the STC[1:0] bits. The division ratio can also be set in the IFC[2:0] and
4. This LSI pauses temporarily and the WDT starts incrementing. The internal and peripheral
5. Supply of the clock that has been set begins at WDT count overflow, and this LSI begins
WDT. The following must be set:
WTCSR.TME = 0: WDT stops
WTCSR.CKS[2:0]: Division ratio of WDT count clock
WTCNT counter: Initial counter value
For setting of the counter, determine the overflow period with the frequency after the
peripheral clock (Pφ) setting change.
PFC[2:0] bits.
clocks both stop and the WDT is supplied with the clock. The clock will continue to be output
at the CK pin. This state is the same as software standby mode. Whether or not registers are
initialized depends on the module. For details, see table 23.4 in section 23, Power-Down
Modes.
operating again. The WDT stops counting after it overflows.
Changing the Frequency
Changing the Multiplication Rate
Rev. 3.00 Mar. 04, 2009 Page 73 of 1168
REJ09B0344-0300