HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 117

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.5
5.5.1
Exception processing can be triggered by trap instruction, illegal slot instructions, and general
illegal instructions, as shown in table 5.9.
Table 5.9
5.5.2
When a TRAPA instruction is executed, trap instruction exception processing starts. The CPU
operates as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
3. The start address of the exception service routine is fetched from the exception processing
Type
Trap instruction
Illegal slot
instructions
General illegal
instructions
instruction to be executed after the TRAPA instruction.
vector table that corresponds to the vector number specified in the TRAPA instruction. That
address is jumped to and the program starts executing. The jump in this case is not a delayed
branch.
Exceptions Triggered by Instructions
Types of Exceptions Triggered by Instructions
Trap Instructions
Types of Exceptions Triggered by Instructions
Source Instruction
TRAPA
Undefined code placed
immediately after a delayed
branch instruction (delay slot) or
instructions that rewrite the PC
Undefined code anywhere
besides in a delay slot
Comment
—
Delayed branch instructions: JMP, JSR,
BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Instructions that rewrite the PC: JMP, JSR,
BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF
—
Rev.4.00 Mar. 27, 2008 Page 71 of 882
5. Exception Processing
REJ09B0108-0400