HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 433

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.4.3
The watchdog timer has a special function to clear software standby mode with an NMI interrupt
or IRQ0 to IRQ7 interrupts. When using software standby mode, set the WDT as described below.
Before Transition to Software Standby Mode: The TME bit in TCSR must be cleared to 0 to
stop the watchdog timer counter before entering software standby mode. The chip cannot enter
software standby mode while the TME bit is set to 1. Set bits CKS2 to CKS0 in TCSR so that the
counter overflow interval is equal to or longer than the oscillation settling time. See section 26.3,
AC Characteristics, for the oscillation settling time.
Recovery from Software Standby Mode: When an NMI signal or IRQ0 to IRQ7 signals are
received in software standby mode, the clock oscillator starts running and TCNT starts
incrementing at the rate selected by bits CKS2 to CKS0 before software standby mode was
entered. When TCNT overflows (changes from H'FF to H'00), the clock is presumed to be stable
and usable; clock signals are supplied to the entire chip and software standby mode ends.
For details on software standby mode, see section 24, Power-Down Modes.
12.4.4
In interval timer mode, when TCNT overflows, the OVF bit of TCSR is set to 1 and an interval
timer interrupt (ITI) is simultaneously requested. Figure 12.4 shows this timing.
Clearing Software Standby Mode
Timing of Setting Overflow Flag (OVF)
φ
TCNT
Overflow signal
(internal signal)
OVF
Figure 12.4 Timing of Setting OVF
H’FF
H’00
Rev.4.00 Mar. 27, 2008 Page 387 of 882
12. Watchdog Timer
REJ09B0108-0400