HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 163

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

[Legend]
x:
Bit
7
6
5
4
3 to 0 —
Bit Name
DTS
CHNE
DISEL
NMIM
Don’t care
Initial Value
Undefined
Undefined
Undefined
Undefined
Undefined
R/W
—
—
—
—
—
Description
DTC Transfer Mode Select
Specifies whether the source or the destination is set
to be a repeat area or block area, in repeat mode or
block transfer mode.
0: Destination is repeat area or block area
1: Source is repeat area or block area
DTC Chain Transfer Enable
When this bit is set to 1, a chain transfer will be
performed.
0: Chain transfer is canceled
1: Chain transfer is set
In data transfer with CHNE set to 1, determination of
the end of the specified number of transfers, clearing
of the activation source flag, and clearing of DTER is
not performed.
DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time a data transfer ends. When this
bit is set to 0, a CPU interrupt request is generated at
the time when the specified number of data transfer
ends.
DTC NMI Mode
This bit designates whether to terminate transfers
when an NMI is input during DTC transfers.
0: Terminate DTC transfer upon an NMI
1: Continue DTC transfer until end of transfer being
Reserved
These bits have no effect on DTC operation. The
write value should always be 0.
executed
Rev.4.00 Mar. 27, 2008 Page 117 of 882
8. Data Transfer Controller (DTC)
REJ09B0108-0400