HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 519

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.3.3
SARX sets the transfer format and stores the second slave address. In slave mode of the I
format, if the FS bit is set to 0 and the upper seven bits of SARX match the upper seven bits of the
first frame received after a start condition, this module operates as the slave device specified by
the master device. SARX can be accessed only when the ICE bit in ICCR is set to 0.
Table 14.2 Transfer Format
Bit
7
6
5
4
3
2
1
0
SAR
FS
0
1
Bit Name
SVAX6
SVAX5
SVAX4
SVAX3
SVAX2
SVAX1
SVAX0
FSX
Second Slave-Address Register (SARX)
SARX
FSX
0
1
0
1
Operating Mode
I
•
•
I
•
•
•
I
•
•
•
Synchronous serial format
•
•
2
2
2
C bus format
C bus format
C bus format
Initial Value
0
0
0
0
0
0
0
1
Enables the slave addresses in SAR and SARX
Enables the general call address
Enables the slave address in SAR
Disables the slave address in SARX
Enables the general call address
Disables the slave address in SAR
Enables the slave address in SARX
Disables the general call address
Disables the slave addresses in SAR and SARX
Disables the general call address
R/W Description
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W Format Select X
Second Slave Address 6 to 0
Set second slave address.
In conjunction with the FS bit in SAR, this bit selects
the transfer format. See table 14.2.
Rev.4.00 Mar. 27, 2008 Page 473 of 882
14. I
2
C Bus Interface (IIC) Option
REJ09B0108-0400
2
C bus