HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 180

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8. Data Transfer Controller (DTC)
8.4
8.4.1
The procedure for using the DTC with interrupt activation is as follows:
1. Set the DTMR, DTCRA, DTSAR, DTDAR, DTCRB, and DTIAR register information in
2. Specify the register information start address with DTBR and the DTC vector table.
3. Set the corresponding DTER bit to 1.
4. The DTC is activated when an interrupt source occurs.
5. When interrupt requests are not made to the CPU, the interrupt source is cleared, but the DTER
6. Interrupt sources are cleared within the CPU interrupt routine. When doing continuous DTC
8.4.2
The procedure for using the DTC with software activation is as follows:
1. Set the DTMR, DTCRA, DTSAR, DTDAR, DTCRB, and DTIAR register information in
2. Set the start address of the register information in the DTBR register and the DTC vector
3. Check that the SWDTE bit is 0.
4. Write 1 to SWDTE bit and the vector number to DTVEC.
5. Check the vector number written to DTVEC.
6. After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested,
7. The SWDTE bit is cleared to 0 within the CPU interrupt routine. For continuous DTC data
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memory space.
is not. When interrupts are requested, the interrupt source is not cleared, but the DTER is.
data transfers, set the DTER to 1 after reading DTER = 0.
memory space.
address.
the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit
to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the
SWDTE bit is held at 1 and a CPU interrupt is requested.
transfer, set the SWDTE bit to 1 after confirming that its current value is 0. Then write the
vector number to DTVEC for continuous DTC transfer.
Procedures for Using DTC
Activation by Interrupt
Activation by Software