HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 775

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• Clearing by the IRQ interrupt input
Note: * If the IRQ pin setting is detection at the falling edge or detection at both rising and
Software Standby Mode Application Example: Figure 24.1 shows an example in which a
transition is made to software standby mode at the falling edge of the NMI pin, and software
standby mode is cleared at a rising edge of the NMI pin.
In this example, when the NMI pin is driven low while the NMI edge select bit (NMIE) in ICR1 is
0 (falling edge specification), an NMI interrupt is accepted. Then, the NMIE bit is set to 1 (rising
edge specification) in the NMI exception service routine, the SSBY bit in SBYCR is set to 1, and
a SLEEP instruction is executed to transfer to software standby mode.
Software standby mode is cleared at the rising edge of the NMI pin.
When the falling edge or rising edge of the IRQ pin (selected by the IRQ7S to IRQ0S bits in
ICR1 of the interrupt controller (INTC) and the IRQ7ES[1:0] to IRQ0ES[1:0] bits in ICR2) is
detected, clock oscillation is started*. This clock pulse is supplied only to the watchdog timer
(WDT). The IRQ interrupt priority level should be higher than the interrupt mask level set in
the status register (SR) of the CPU before the transition to software standby mode.
After the elapse of the time set in the clock select bits (CKS2 to CKS0) in TCSR of the WDT
before the transition to software standby mode, the WDT overflow occurs. Since this overflow
indicates that the clock has been stabilized, clock pulse will be supplied to the entire chip after
this overflow. Software standby mode is thus cleared and the IRQ exception handling is
started.
When clearing software standby mode by the IRQ interrupt, set CKS2 to CKS0 bits so that the
WDT overflow period will be longer than the oscillation stabilization time.
When software standby mode is cleared by the falling edge or both rising and falling edges of
the IRQ pin, the IRQ pin should be high when the CPU enters software standby mode (when
the clock pulse stops) and should be low when the CPU returns from software standby mode
(when the clock is initiated after the oscillation stabilization). When software standby mode is
cleared by the rising edge of the IRQ pin, the IRQ pin should be low when the CPU enters
software standby mode (when the clock pulse stops) and should be high when the CPU returns
from software standby mode (when the clock is initiated after the oscillation stabilization).
falling edges, clock oscillation starts at the falling edge detection. If the setting is
detection at the rising edge, it starts at the rising edge detection. Do not set the IRQ pin
to detection at the low level.
Rev.4.00 Mar. 27, 2008 Page 729 of 882
24. Power-Down Modes
REJ09B0108-0400