HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 573
HD64F7144F50V
Manufacturer Part Number
HD64F7144F50V
Description
IC SUPERH MCU FLASH 256K 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Specifications of HD64F7144F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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HD64F7144F50V
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- Current page: 573 of 932
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Scope of Initialization:
The initialization executed by this function covers the following items:
• ICDRE and ICDRF internal flags
• Transmit/receive sequencer and internal operating clock counter
• Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data
The following items are not initialized:
• Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, SCRX (except for the
• Internal latches used to retain register read information for setting/clearing flags in the ICMR,
• The value of the ICMR register bit counter (BC2 to BC0)
• Generated interrupt sources (interrupt sources transferred to the interrupt controller)
Notes on Initialization:
• Interrupt flags and interrupt sources are not cleared; therefore, flag clearing measures must be
• Basically, other register flags are not cleared either; therefore, flag clearing measures must be
• If a flag clearing setting is made during transmission/reception, the IIC module will stop
The value of the BBSY bit cannot be modified directly by this module clear function, but since pin
waveforms with stop condition may be generated depending on the state and release timing of the
SCL and SDA pins, causing the BBSY bit to be cleared. Similarly, switching of the state may
influence other bits and flags.
To prevent problems caused by these factors, the following procedure should be used when
initializing the IIC state.
1. Execute initialization of the internal state by clearing the ICE bit.
2. Execute a stop condition issue instruction (write 0 to BBSY and SCP) to clear the BBSY bit to
3. Re-execute initialization of the internal state by clearing the ICE bit.
4. Initialize (reset) the IIC registers.
output, etc.)
ICDRE and ICDRF flags)
ICCR, and ICSR registers
taken as necessary.
taken as necessary.
transmitting/receiving at that point and the SCL and SDA pins will be released. When
transmission/reception is started again, register initialization, etc., must be carried out as
necessary to enable correct communication as a system.
0, and wait for two transfer rate clock cycles.
Rev.4.00 Mar. 27, 2008 Page 527 of 882
14. I
2
C Bus Interface (IIC) Option
REJ09B0108-0400
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