HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 316

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.
Example of Cascaded Operation Setting Procedure: Figure 11.18 shows an example of the
setting procedure for cascaded operation.
Examples of Cascaded Operation: Figure 11.19 illustrates the operation when TCNT_2
overflow/underflow counting has been set for TCNT_1 and phase counting mode has been
designated for channel 2.
TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
Rev.4.00 Mar. 27, 2008 Page 270 of 882
REJ09B0108-0400
Multi-Function Timer Pulse Unit (MTU)
TCLKC
TCLKD
TCNT_2
TCNT_1
<Cascaded operation>
Cascaded operation
Set cascading
Figure 11.18
Start count
FFFD
Figure 11.19
0000
FFFE
FFFF
[1]
[2]
Cascaded Operation Setting Procedure
Example of Cascaded Operation
0000
[1] Set bits TPSC2 to TPSC0 in the channel 1
[2] Set the CST bit in TSTR for the upper and
0001
TCR to B'1111 to select TCNT_2 overflow/
underflow counting.
lower channel to 1 to start the count
operation.
0001
0002
0001
0000
FFFF
0000