HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 358
![IC SUPERH MCU FLASH 256K 112QFP](/photos/12/21/122194/hd64f7144f50v_sml.jpg)
HD64F7144F50V
Manufacturer Part Number
HD64F7144F50V
Description
IC SUPERH MCU FLASH 256K 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Specifications of HD64F7144F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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11.
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is
set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare
match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The
MTU has 16 input capture/compare match interrupts, four each for channels 0, 3, and 4, and two
each for channels 1 and 2.
Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the
TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt
request is cleared by clearing the TCFV flag to 0. The MTU has five overflow interrupts, one for
each channel.
Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the
TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt
request is cleared by clearing the TCFU flag to 0. The MTU has two underflow interrupts, one
each for channels 1 and 2.
11.5.2
DTC Activation: The DTC can be activated by the TGR input capture/compare match interrupt in
each channel. For details, see section 8, Data Transfer Controller (DTC).
A total of 17 MTU input capture/compare match interrupts can be used as DTC activation sources,
four each for channels 0 and 3, and two each for channels 1 and 2, and five for channel 4.
DMAC Activation: The DMAC can be activated by the TGRA input capture/compare match
interrupt in each channel. For details, see section 10, Direct Memory Access Controller (DMAC).
A total of five MTU input capture/compare match interrupts can be used as DMAC activation
sources, one for each channel.
11.5.3
The A/D converter can be activated by the TGRA input capture/compare match in each channel.
If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a
TGRA input capture/compare match on a particular channel, a request to start A/D conversion is
sent to the A/D converter. If the MTU conversion start trigger has been selected on the A/D
converter at this time, A/D conversion starts.
In the MTU, a total of five TGRA input capture/compare match interrupts can be used as A/D
converter conversion start sources, one for each channel.
Rev.4.00 Mar. 27, 2008 Page 312 of 882
REJ09B0108-0400
Multi-Function Timer Pulse Unit (MTU)
DTC/DMAC Activation
A/D Converter Activation
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