HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 149

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.2
The UBC has the following registers. For details on register addresses and register states during
each processing, refer to section 25, List of Registers.
• User break address register H (UBARH)
• User break address register L (UBARL)
• User break address mask register H (UBAMRH)
• User break address mask register L (UBAMRL)
• User break bus cycle register (UBBR)
• User break control register (UBCR)
7.2.1
The user break address register (UBAR) consists of two registers: user break address register H
(UBARH) and user break address register L (UBARL). Both are 16-bit readable/writable registers.
UBARH specifies the upper bits (bits 31 to 16) of the address for the break condition, while
UBARL specifies the lower bits (bits 15 to 0).
The initial value of UBAR is H'00000000.
• UBARH Bits 15 to 0: specifies user break address 31 to 16 (UBA31 to UBA16)
• UBARL Bits 15 to 0: specifies user break address 15 to 0 (UBA15 to UBA0)
7.2.2
The user break address mask register (UBAMR) consists of two registers: user break address mask
register H (UBAMRH) and user break address mask register L (UBAMRL). Both are 16-bit
readable/writable registers. UBAMRH specifies whether to mask any of the break address bits set
in UBARH, and UBAMRL specifies whether to mask any of the break address bits set in UBARL.
• UBAMRH Bits 15 to 0: specifies user break address mask 31 to 16 (UBM31 to UBM16)
• UBAMRL Bits 15 to 0: specifies user break address mask 15 to 0 (UBM15 to UBM0)
Register Descriptions
User Break Address Register (UBAR)
User Break Address Mask Register (UBAMR)
Rev.4.00 Mar. 27, 2008 Page 103 of 882
7. User Break Controller (UBC)
REJ09B0108-0400