HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 554

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14. I
11. Clear the IRIC flag to 0.
12. The IRIC flag is set to 1 according to the following two conditions.
13. Read the IRTR flag in ICSR.
14. When the IRTR flag is 0, clear the IRIC flag to 0 to cancel the wait operation.
15. Clear the WAIT bit in ICMR to 0 to cancel the wait mode, and then clear the IRIC flag to 0.
16. Read the final receive data in ICDR.
17. Write BBSY = 0 and SCP = 0 to ICCR. When SCL is high, SDA is driven from low to high,
Rev.4.00 Mar. 27, 2008 Page 508 of 882
REJ09B0108-0400
User processing
(Master output)
(Master output)
(Slave output)
A. The IRIC flag is set to 1 at the falling edge of the 8th cycle of one frame of the receive
B. The IRIC flag is set to 1 at the rising edge of the 9th cycle of one frame of the receive
When the IRTR flag is 0, cancel wait mode by clearing the IRIC flag as described in step 14.
When the IRTR flag is 1 and the receive operation has been completed, issue the stop
condition as described in step 15.
To detect the completion of receive operation, go back to step 12 and read the IRIC flag.
Clear the IRIC flag while WAIT is 0. (If the stop condition issuance instruction is executed by
clearing the WAIT bit to 0 after clearing the IRIC flag to 0, the stop condition may not be
output normally.)
and the stop condition is generated.
Master transmit mode
2
SCL
SDA
SDA
IRTR
ICDR
IRIC
C Bus Interface (IIC) Option
Figure 14.15 An Example of the Timing of Operations in Master Receive Mode
clock.
SCL is automatically fixed low in synchronization with the internal clock until the IRIC
flag is cleared.
clock.
The IRTR and ICDRF flags are set to 1, indicating that one frame of data have been
completely received. The master devise continues outputting the receive clock for the next
receive data.
A
9
[1] Clear TRS
and IRIC to 0
Master receive mode
bit 7
1
[2] ICDR read (dummy read)
bit 6
2
(MLS = ACKB = 0, WAIT = 1)
bit 5
3
Data 1
bit 4
4
bit 3
5
bit 2
6
bit 1
7
bit 0
8
[3]
[
4
]
[6] IRIC clear
IRTR=0
(wait cancelled)
A
[5] ICDR read
[3]
[
9
4
(data 1)
]
IRTR=1
bit 7
1
bit 6
[6] IRIC clear
2
Data 1
Data 2
bit 5
3
bit 4
4
bit 3
5