HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 52

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1. Overview
1.3
Rev.4.00 Mar. 27, 2008 Page 6 of 882
REJ09B0108-0400
PE1/TIOC0B/DRAK0/TRST *
PE0/TIOC0A/DREQ0/TMS*
PE3/TIOC0D/DRAK1/TDO *
PE2/TIOC0C/DREQ1/TDI *
PE4/TIOC1A/RXD3/TCK *
PE13/TIOC4B/MRES
PE11/TIOC3D/RXD3
PE10/TIOC3C/TXD2
PE12/TIOC4A/TXD3
ASEBRKAK Processing
Notes :
PE6/TIOC2A/SCK3
PE7/TIOC2B/RXD2
PE8/TIOC3A/SCK2
PE9/TIOC3B/SCK3
PE5/TIOC1B/TXD3
Pin Arrangement
Product type
Masked ROM version and ROM less version
F-ZTAT version (when using E10A)
F-ZTAT version (Not when using E10A)
1. Fixed as Vcc in the masked ROM version and ROM less version, and used as an FWP input pin in the F-ZTAT version (used as an FWE in
2. Used for E10A debugging mode. Used as an ASEBRKAK output pin in the F-ZTAT version. Refer to the table below for
3. Used for E10A debugging mode. Fixed to Vss in the masked ROM version and ROM less version, or used as a DBGMD input pin in the
4. Valid only in the F-ZTAT version (invalid only in the masked ROM version and ROM less version).
5. Valid only in the masked ROM version and ROM less version (invalid in the F-ZTAT version and emulator).
PF0/AN0
PF1/AN1
PF2/AN2
PF3/AN3
PF4/AN4
PF5/AN5
PF6/AN6
PF7/AN7
programmer mode).
processing the ASEBRKAK pin.
F-ZTAT version.
AVss
AVcc
Vss
Vss
Vcc
Vss
4
4
4
4
4
100
101
102
103
104
105
106
107
108
109
110
111
112
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
1
2
3
Figure 1.3 SH7144 Pin Arrangement
4
5
Fixed to Vcc
Yes
No
Yes
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Fixed to Vss
Yes
No
Yes
(Top view)
QFP-112
Processing
Pull-up
Yes
Yes
Yes
Pull-down
Yes
No
Yes
NC
No
No
No
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PD12/D12/AUDRST*
Vss
PD13/D13/AUDMD*
PD14/D14/AUDCK*
PD15/D15/AUDSYNC*
PA0/RXD0
PA1/TXD0
PA2/SCK0/DREQ0/IRQ0
PA3/RXD1
PA4/TXD1
PA5/SCK1/DREQ1/IRQ1
PA6/TCLKA/CS2
PA7/TCLKB/CS3
PA8/TCLKC/IRQ2
PA9/TCLKD/IRQ3
PA10/CS0
PA11/CS1
Vss
PA12/WRL
Vcc
PA13/WRH
WDTOVF
PA14/RD
Vss(DBGMD*
PB9/IRQ7/A21/ADTRG
PB8/IRQ6/A20/WAIT
PB7/IRQ5/A19/BREQ
PB6/IRQ4/A18/BACK
3
)
4
4
4
4