HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 744

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22. User Debugging Interface (H-UDI)
22.3.2
The status register (SDSR) is a 16-bit register that can be read and written to by the CPU. The
SDSR value can be output from TDO, but serial data cannot be written to SDSR via TDI. The
SDTRF bit is output by means of a one-bit shift. In a two-bit shift, the SDTRF bit is output first,
followed by a reserved bit.
SDSR is initialized by TRST signal input, but is not initialized in software standby mode.
Rev.4.00 Mar. 27, 2008 Page 698 of 882
REJ09B0108-0400
Bit
15 to 12 ⎯
11
10 to 1
0
Status Register (SDSR)
Bit Name Initial value R/W Description
⎯
⎯
SDTRF
All 0
1
All 0
1
R
R
R
R/W Serial Data Transfer Control Flag
Reserved
These bits are always read as 0. The write value should
always be 0.
Reserved
This bit is always read as 1. The write value should
always be 1.
Reserved
These bits are always read as 0. The write value should
always be 0.
Indicates whether H-UDI registers can be accessed by
the CPU. The SDTRF bit is initialized by the TRST
signal, but is not initialized in software standby mode.
0: Serial transfer to SDDR has ended, and SDDR can be
1: Serial transfer to SDDR is in progress
accessed