HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 499

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

bits in SDCR to 0. According to smart card regulations, clear the O/E bit in SMR to 0 to select
even parity mode.
With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to
state Z, and transfer is performed in MSB-first order. The above start character data is H'3F. For
the inverse convention type, set the DIR and SINV bits in SDCR to 1. According to smart card
regulations, even parity mode is the logic 0 level of the parity bit, and corresponds to state Z. In
this LSI, the SINV bit inverts only data bits D0 to D7. Therefore, set the O/E bit in SMR to 1 to
invert the parity bit for both transmission and reception.
13.7.3
Operation in block transfer mode is the same as that in the normal smart card interface mode,
except for the following points.
• In reception, though the parity check is performed, no error signal is output even if an error is
• In transmission, a guard time of at least 1 etu is left between the end of the parity bit and the
• In transmission, because retransmission is not performed, the TEND flag is set to 1, 11.5 etu
• As with the normal smart card interface, the ERS flag indicates the error signal status, but
detected. However, the PER bit in SSR is set to 1 and must be cleared before receiving the
parity bit of the next frame.
start of the next frame.
after transmission start.
since error signal transfer is not performed, this flag is always cleared to 0.
Block Transfer Mode
Figure 13.24 Inverse Convention (DIR = SINV = O/E = 1)
(Z)
Ds
A
D7
Z
D6
Z
D5
A
D4
A
D3
A
D2
A
D1
A
13. Serial Communication Interface (SCI)
Rev.4.00 Mar. 27, 2008 Page 453 of 882
D0
A
Dp
Z
(Z)
State
REJ09B0108-0400