HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 525

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
3
2
0
Bit Name
ACKE
BBSY
SCP
Initial Value
0
0
1
R/W Description
R/W Enables/Disables Acknowledge Bit
R/W
W
0: The value of the acknowledge bit is ignored to allow
1: When the value of the acknowledge bits received in
The acknowledge bit is used in two different ways,
depending on the situation. One case is that the
acknowledge bit is used as a kind of flag to indicate
whether or not processing for the reception of data has
been completed.
The other case is that acknowledge bit is fixed to 1.
Bus Busy
Start/Stop Condition Issuance Disable
Master mode:
•
•
Slave mode:
•
[BBSY setting condition]
•
[BBSY clearing condition]
•
The start and stop conditions are issued by using the
MOV instruction.
The I
mode before the start condition is issued. Before writing
1 to BBSY and 0 to SCP, set MST and TRS to 1.
The BBSY flag may be read to confirm whether or not
the I
The SCP bit is always read as 1. Data is not stored even
if 0 is written to the SCP bit.
the continuous transfer of data. The received value of
the acknowledge bits that are received do not affect
the ACKB bit; the value in the ACKB bit in ICSR
remains at 0.
the I
Write 0 to BBSY and SCP: Issuing stop condition
Write 1 to BBSY and 0 to SCP: Issuing start
condition and re-transmitting start condition
Writing to the BBSY flag is disabled
When SDA changes from high to low while SCL is
high, the system regards the start condition as
having been set.
When SDA changes from low to high while SDA is
high, the system regards the stop condition as
having been set.
2
C bus (SCL, SDA) has been released.
2
C bus interface must be set to master transmit
2
C bus format is 1, transmission is suspended.
Rev.4.00 Mar. 27, 2008 Page 479 of 882
14. I
2
C Bus Interface (IIC) Option
REJ09B0108-0400