HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 168

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8. Data Transfer Controller (DTC)
8.3
8.3.1
The DTC operates when activated by an interrupt or by a write to DTCSR by software. An
interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTER
bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the
activation source interrupt flag or corresponding DTER bit is cleared. The activation source flag,
in the case of RXI_2, for example, is the RDRF flag of SCI2.
When a DTC is activated by an interrupt, existing CPU mask level and interrupt controller
priorities have no effect. If there is more than one activation source at the same time, the DTC
operates in accordance with the default priorities.
Figure 8.2 shows a block diagram of activation source control. For details see section 6, Interrupt
Controller (INTC).
8.3.2
Figure 8.3 shows the allocation of register information in memory space. The register information
start addresses are designated by DTBR for the upper 16 bits, and the DTC vector table for the
lower 16 bits.
The allocation in order from the register information start address in normal mode is DTMR,
DTCRA, 4 bytes empty (no effect on DTC operation), DTSAR, then DTDAR. In repeat mode it is
DTMR, DTCRA, DTIAR, DTSAR, and DTDAR. In block transfer mode, it is DTMR, DTCRA, 2
bytes empty (no effect on DTC operation), DTCRB, DTSAR, then DTDAR.
Fundamentally, certain RAM areas are designated for addresses storing register information.
Rev.4.00 Mar. 27, 2008 Page 122 of 882
REJ09B0108-0400
Operation
Activation Sources
Location of Register Information and DTC Vector Table
IRQ
on-chip
peripheral
Figure 8.2 Activating Source Control Block Diagram
Interrupt
requests
flag clear
Source flag clear
Source
DMAC
Interrupt requests
(those not designated as
DMAC activating sources)
Clear
DTC control
DTER
DTC
DTC activation
request
CPU interrupt requests
(those not designated as
DTC activating sources)
INTC