HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 570
![IC SUPERH MCU FLASH 256K 112QFP](/photos/12/21/122194/hd64f7144f50v_sml.jpg)
HD64F7144F50V
Manufacturer Part Number
HD64F7144F50V
Description
IC SUPERH MCU FLASH 256K 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Specifications of HD64F7144F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Company:
Part Number:
HD64F7144F50V
Manufacturer:
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2
14. I
C Bus Interface (IIC) Option
14.4.8
DTC Operation
This LSI provides the DTC to allow continuous data transfer. The DTC is initiated when the IRTR
flag is set to 1, which is one of the two interrupt flags (IRIC and IRTR). When the ACKE bit is 0,
the ICDRE, IRIC, and IRTR flags are set at the end of data transmission regardless of the
acknowledge bit value. When the ACKE bit is 1, the ICDRE, IRIC, and IRTR flags are set if data
transmission is completed with the acknowledge bit value of 0, or only the IRIC flag is set if data
transmission is completed with the acknowledge bit value of 1.
When initiated, DTC transfers specified number of bytes, clears the ICDRE, IRIC, and IRTR flags
to 0. Therefore, no interrupt is generated during continuous data transfer; however, if data
transmission is completed with the acknowledge bit value of 1 when the ACKE bit is 1, DTC is
not initiated, thus allowing an interrupt to be generated if enabled.
The acknowledge bit may indicate specific events such as completion of receive processing for
some receiving device, and for other receiving device, the acknowledge bit may be held to 1,
indicating no specific event.
2
In the I
C bus format, since the slave device or the direction of transfer is selected by the slave
address or the R/W bit, and the acknowledge bit may indicate the end of reception or reception of
the final frame, the continuous transfer of data by the DTC must be combined with interrupt-
driven processing by the CPU.
Table 14.7 shows examples of processes in which the DTC is used. For the slave-mode processes,
it is assumed that the amount of data to be transferred is defined in advance.
Rev.4.00 Mar. 27, 2008 Page 524 of 882
REJ09B0108-0400
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