HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 460

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13. Serial Communication Interface (SCI)
Note:
Rev.4.00 Mar. 27, 2008 Page 414 of 882
REJ09B0108-0400
Bit
2
1
0
*
Bit Name Initial Value R/W
TEND
MPB
MPBT
Only 0 can be written to clear the flag.
1
0
0
R
R
R/W
Description
Transmit End
This bit is set to 1 when no error signal has been sent
back from the receive side and the next transmit data is
ready to be transferred to TDR.
[Setting conditions]
•
•
•
The timing of bit setting differs according to the register
setting as follows:
When GM = 0 and BLK = 0, 2.5 etu after transmission
starts
When GM = 0 and BLK = 1, 1.0 etu after transmission
starts
When GM = 1 and BLK = 0, 1.5 etu after transmission
starts
When GM = 1 and BLK = 1, 1.0 etu after transmission
starts
[Clearing conditions]
•
•
•
Multiprocessor
This bit is not used in smart card interface mode.
Multiprocessor Bit Transfer
Write 0 to this bit in smart card interface mode.
Power-on reset or software standby mode
When the TE bit in SCR is 0 and the ESR bit is also 0
When the ESR bit is 0 and the TDRE bit is 1 after the
specified interval following transmission of 1-byte data
When 0 is written to TDRE after reading TDRE = 1
When the DMAC is activated by a TXI interrupt
When the DTC is activated by a TXI interrupt and
transmit data is transferred to TDR while the DISEL
bit in DTMR of the DTC is 0