HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 222

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10. Direct Memory Access Controller (DMAC)
Bit
6
5
4
3
2
Rev.4.00 Mar. 27, 2008 Page 176 of 882
REJ09B0108-0400
Bit Name
DS
TM
TS1
TS0
IE
Initial Value
0
0
0
0
0
R/W
(R/W)*
R/W
R/W
R/W
R/W
2
Description
DREQ Select
Sets the sampling method for the DREQ pin in
external request mode to either low-level detection or
falling-edge detection. This bit is valid only with
CHCR_0 and CHCR_1. For CHCR_2 and CHCR_3,
this bit is always read as 0 and the write value should
always be 0.
Even with channels 0 and 1, when specifying an on-
chip peripheral module or auto-request as the transfer
request source, this bit setting is ignored. The
sampling method is fixed at falling-edge detection in
cases other than auto-request.
0: Low-level detection
1: Falling-edge detection
Transfer Mode
Specifies the bus mode for data transfer.
0: Cycle steal mode
1: Burst mode
Transfer Size 1, 0
Specify size of data for transfer.
00: Specifies byte size (8 bits)
01: Specifies word size (16 bits)
10: Specifies longword size (32 bits)
11: Prohibited
Interrupt Enable
When this bit is set to 1, interrupt requests are
generated after the number of data transfers
specified in the DMATCR (when TE = 1).
0: Interrupt request not generated after DMATCR-
1: Interrupt request enabled on completion of
specified transfer count
DMATCR specified number of transfers