HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 195
HD64F7144F50V
Manufacturer Part Number
HD64F7144F50V
Description
IC SUPERH MCU FLASH 256K 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Specifications of HD64F7144F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F7144F50V
Manufacturer:
RENESAS
Quantity:
450
Company:
Part Number:
HD64F7144F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7144F50V
Manufacturer:
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Quantity:
20 000
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Bit
7
6
Bit Name Initial Value R/W
CW3
CW2
1
1
R/W
R/W
Description
Idle cycles at continuous access to CS3 and CS7 spaces
This bit inserts an idle cycle and negates the CS3 signal to
make the bus cycle end obvious when accessing the CS3
space continuously. An idle cycle set by this bit is also
inserted when access is made to the CS7 space after
access to the CS3 space. In addition, an idle cycle set by
this bit is inserted when continuous access is made to the
CS7 space, and when access is made to the CS3 space
after access to the CS7 space.
0: No idle cycle inserted at continuous access to the CS3
1: One idle cycle inserted at continuous access to the CS3
When the write cycle follows the read cycle, the larger of
the value specified with IW and that specified with CW is
used as the idle cycles to be inserted.
Idle cycles at continuous access to CS2 and CS6 spaces
This bit inserts an idle cycle and negates the CS2 signal to
make the bus cycle end obvious when accessing the CS2
space continuously. An idle cycle set by this bit is also
inserted when access is made to the CS6 space after
access to the CS2 space. In addition, an idle cycle set by
this bit is inserted when continuous access is made to the
CS6 space, and when access is made to the CS2 space
after access to the CS6 space.
0: No idle cycle inserted at continuous access to the CS2
1: One idle cycle inserted at continuous access to the CS2
When the write cycle follows the read cycle, the larger of
the value specified with IW and that specified with CW is
used as the idle cycles to be inserted.
and CS7 spaces.
and CS7 spaces.
and CS6 spaces.
and CS6 spaces.
Rev.4.00 Mar. 27, 2008 Page 149 of 882
9. Bus State Controller (BSC)
REJ09B0108-0400
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