HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 517

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.3
The I
registers and the states of the registers in each state of processing, refer to section 25, List of
Registers. Registers ICDR and SARX and registers ICMR and SAR are allocated to the same
addresses, and accessible registers differ depending on the state of ICE bit in ICCR. When the ICE
bit is 0, SAR and SARX can be accessed, and when the ICE bit is 1, ICMR and ICDR can be
accessed.
• I
• I
• I
• I
• Slave-address register (SAR)
• Second slave-address register (SARX)
• Serial control register X (SCRX)
14.3.1
ICDR is an 8-bit readable/writable register that holds the data for transmission during
transmission, and holds the received data during reception. Internally, ICDR consists of a shift
register (ICDRS), receive buffer (ICDRR), and transmission buffer (ICDRT).
Data is automatically transferred between these three registers according to the bus state; this
affects the states of flags, such as the ICDRF flag in SCRX and the internal flag ICDRE.
In master transmit mode of the I
after start condition is detected. When the start condition is detected, previous write data is
ignored. In slave transmit mode, writing should be performed after the slave addresses match and
the TRS bit is automatically changed to 1.
When I
is 0), data is transferred automatically from ICDRT to ICDRS after successful transmission of one
frame of data using ICDRS. When the ICDRE flag is 1 and the next transmit data writing is
waited, data is transferred automatically from ICDRT to ICDRS by writing to ICDR. In receive
mode (TRS = 0), no data is transferred from ICDRT to ICDRS. Note that data should not be
written to ICDR in receive mode.
Reading receive data from ICDR is performed after data is transferred from ICDRS to ICDRR.
2
2
2
2
C bus control register (ICCR)
C bus status register (ICSR)
C bus data register (ICDR)
C bus mode register (ICMR)
2
C bus interface includes the following registers for each channel. For the addresses of these
2
C is in transmit mode (TRS = 1) and the next transmit data is in ICDRT (the ICDRE flag
Description of Registers
I
2
C Bus Data Register (ICDR)
2
C bus format, writing transmit data to ICDR should be performed
Rev.4.00 Mar. 27, 2008 Page 471 of 882
14. I
2
C Bus Interface (IIC) Option
REJ09B0108-0400