HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 236

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10. Direct Memory Access Controller (DMAC)
Dual Address Mode:
Dual address mode is used for access of both the transfer source and destination by address.
Transfer source and destination can be accessed either internally or externally. Dual address mode
is subdivided into two other modes: direct address transfer mode and indirect address transfer
mode.
• Direct Address Transfer Mode
Rev.4.00 Mar. 27, 2008 Page 190 of 882
REJ09B0108-0400
Data is read from the transfer source during the data read cycle, and written to the transfer
destination during the write cycle, so transfer is conducted in two bus cycles. At this time, the
transfer data is temporarily stored in the DMAC. With the kind of external memory transfer
shown in figure 10.6, data is read from one of the memories by the DMAC during a read cycle,
then written to the other external memory during the subsequent write cycle. Figure 10.7
shows the timing for this operation.
Figure 10.6 Direct Address Operation during Dual Address Mode
2nd bus cycle
1st bus cycle
The SAR value is taken as the address, and data is read from the transfer source
module and stored temporarily in the DMAC.
The DAR value is taken as the address, and data stored in the DMAC's data
buffer is written to the transfer destination module.
Data buffer
Data buffer
DMAC
DMAC
SAR
DAR
SAR
DAR
Transfer destination
Transfer destination
Transfer source
Transfer source
Memory
Memory
module
module
module
module