HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 518

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14. I
When I
is transferred automatically from ICDRS to ICDRR, following reception of one frame of data
using ICDRS. When additional data is received while the ICDRF flag is 1, data is transferred
automatically from ICDRS to ICDRR by reading from ICDR. In transmit mode, no data is
transferred from ICDRS to ICDRR. Always set I
When, excluding the acknowledge bit, there are fewer than 8 bits in one frame, the alignment of
the data for transmission and of received data varies according to the setting of the MLS bit in
ICMR. Data for transmission should span the selected number of bits from the MSB when MLS =
0. When MLS is 1, the data should span the selected number of bits from the LSB. Received data
is read from the LSB when MLS is 0 and from the MSB when MLS is 1.
ICDR is only accessible when the ICE bit in ICCR is set to 1. The ICDR is undefined at reset.
14.3.2
SAR sets the transfer format and stores the slave address. In slave mode of the I
the FS bit is set to 0 and the upper seven bits of SAR match the upper seven bits of the first frame
received after a start condition, this module operates as the slave device specified by the master
device. SAR can be accessed only when the ICE bit in ICCR is set to 0.
Rev.4.00 Mar. 27, 2008 Page 472 of 882
REJ09B0108-0400
Bit
7
6
5
4
3
2
1
0
2
C Bus Interface (IIC) Option
2
C is in receive mode and no previous data remains in ICDRR (the ICDRF flag is 0), data
Slave-Address Register (SAR)
Bit Name
SVA6
SVA5
SVA4
SVA3
SVA2
SVA1
SVA0
FS
0
0
0
0
0
0
0
0
Initial Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Slave Address 6 to 0
Set slave address.
Format Select
In conjunction with the FSX bit in SARX, this bit
selects the transfer format. See table 14.2.
To identify the general call address, this bit should
always be set to 0.
2
C to receive mode before reading from ICDR.
2
C bus format, if