HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 544

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14. I
The following description gives the procedures to transmit data serially in synchronization with
ICDR (ICDRT) writing operation.
1. Perform initialization according to the procedure described in section 14.4.2, Initialization.
2. Confirm that the bus is free by reading the BBSY flag in ICCR.
3. Set the MST and TRS bits in ICCR to 1 to select the master transmit mode.
4. Then write 1 to BBSY and 0 to SCP. This changes the level on SDA from high to low while
5. With the generation of the start condition, the IRIC and IRTR flags are set to 1. When the IEIC
6. Write the data (slave address + R/W) to ICDR after the start condition is detected.
7. When the transmission of one frame has been completed, the IRIC flag is set to 1 on the rising
8. Read the ACKB bit in ICSR to confirm ACKB = 0.
9. Write the transmit data to ICDR.
10. When the transmission of one frame has been completed, the IRIC flag is set to 1 on the rising
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SCL is high, and is thus the generation of the start condition.
bit in ICCR has been set to 1, an interrupt request is generated for the CPU.
In the I
data following the start condition indicates the 7-bit slave address and transmit/receive
direction (R/W).
To determine the end of the transfer, the IRIC flag is cleared to 0.
After writing to ICDR, clear IRIC continuously in order that no other interrupt processing is
executed. If the time for transmission of one frame of data has passed before the IRIC flag
clearing, the end of transmission cannot be determined.
The master device transmits the transmit clock signal and the data written in the ICDR. To
acknowledge its selection, the slave device that has been selected (that matches the slave
address) sets the level on SDA low in the 9th cycle of the transmit clock.
edge of the 9th cycle of the transmit clock. The level on SCL is automatically fixed low in
synchronization with the internal clock until the next data for transmission has been written to
ICDR.
When the slave device does not return acknowledgement and ACKB = 1, execute transmit end
processing in step 12 and carry out transmission again.
The IRIC flag is cleared to 0 to determine the end of the transfer.
Perform the ICDR writing and the IRIC flag clearing sequentially as in step 6.
Transmission of the next frame is performed in synchronization with the internal clock.
edge of the 9th cycle of the transmit clock. The level on SCL is automatically fixed low in
synchronization with the internal clock until the next data for transmission has been written to
ICDR.
2
C Bus Interface (IIC) Option
2
C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first frame