HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 607

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.2.2
The compare match timer control/status register (CMCSR) is a 16-bit register that indicates the
occurrence of compare matches, sets the enable/disable status of interrupts, and establishes the
clock used for incrementation.
Note:
Bit
15 to 8 ⎯
7
6
5 to 2
1
0
*
Bit Name Initial Value
CMF
CMIE
⎯
CKS1
CKS0
Compare Match Timer Control/Status Register_0, 1 (CMCSR_0, CMCSR_1)
Only 0 can be written for flag clearing.
All 0
0
0
All 0
0
0
R/W
R
R/(W)* Compare Match Flag
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
This flag indicates whether or not the CMCNT and
CMCOR values have matched.
0: CMCNT and CMCOR values have not matched
1: CMCNT and CMCOR values have matched
[Clearing condition]
•
•
Compare Match Interrupt Enable
This bit selects whether to enable or disable a
compare match interrupt (CMI) when the CMCNT
and CMCOR values have matched (CMF = 1).
0: Compare match interrupt (CMI) disabled
1: Compare match interrupt (CMI) enabled
Reserved
These bits are always read as 0. The write value
should always be 0.
These bits select the clock input to CMCNT from
among the four internal clocks obtained by dividing
the peripheral clock (Pφ). When the STR bit of
CMSTR is set to 1, CMCNT begins incrementing with
the clock selected by CKS1 and CKS0.
00: Pφ/8
01: Pφ/32
10: Pφ/128
11: Pφ/512
Write 0 to CMF after reading 1 from it
When the DTC is activated by an CMI interrupt
and data is transferred with the DISEL bit in
DTMR of DTC = 0
Rev.4.00 Mar. 27, 2008 Page 561 of 882
16. Compare Match Timer (CMT)
REJ09B0108-0400