M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 104

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
10.5 Interrupt Control
Figure 10.3 Interrupt Control Registers (1)
The following describes how to enable/disable the maskable interrupts, and how to set the priority in which
order they are accepted. What is explained here does not apply to non-maskable interrupts.
Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in the each interrupt control register to
enable/disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in the
each interrupt control register.
Figures 10.3 and 10.4 show the Interrupt Control Registers.
Interrupt Control Register
NOTES:
b7
1. To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that
2. Use the IFSR07 bit in the IFSR0 register to select.
3. Use the IFSR06 bit in the IFSR0 register to select.
4. This bit can only be reset by writing 0 (do not write 1).
5. When the IFSR02 bit in the IFSR0 register = 0 (CAN0/1 wake-up or error), CAN0/1 wake-up is selected.
6. When the IFSR02 bit = 0, CAN0/1 error is selected. When the IFSR02 bit = 1, CAN1 wake-up/error is selected.
7. Use the IFSR01 bit in the IFSR0 register to select.
Apr 14, 2006
b6
register. For details, refer to 23.6 Interrupts.
When the IFSR02 bit = 1 (CAN0 wake-up/error or CAN1 wake-up/error), CAN0 wake-up/error is selected.
b5
b4
b3
b2
page 80 of 376
b1
b0
Bit Symbol
(b7-b4)
ILVL0
ILVL1
ILVL2
(1)
IR
-
C01WKIC
C0RECIC
C0TRMIC
TB5IC
TB4IC/U1BCNIC
TB3IC/U0BCNIC
U2BCNIC
DM0IC, DM1IC
C01ERRIC
ADIC/KUPIC
S0TIC to S2TIC
S0RIC to S2RIC
TA0IC to TA4IC
TB0IC to TB2IC
Symbol
Interrupt priority level
select bits
Interrupt request bit
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
(5)
(6)
(7)
Bit Name
(2)
(3)
0041h
0042h
0043h
0045h
0046h
0047h
004Ah
004Bh, 004Ch
004Dh
004Eh
0051h, 0053h, 004Fh
0052h, 0054h, 0050h
0055h to 0059h
005Ah to 005Ch
Address
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : Interrupt not requested
1 : Interrupt requested
Function
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
After Reset
10. Interrupts
RW
RW
RW
RW
RW
-
(4)