M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 282

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
21.3.3.1 FMR00 Bit
21.3.3.2 FMR01 Bit
21.3.3.3 FMR02 Bit
21.3.3.4 FMSTP Bit
21.3.3.5 FMR05 Bit
21.3.3.6 FMR06 Bit
This bit indicates the operating status of the flash memory. It is set to 0 while the program, block erase,
erase all unlocked block, lock bit program, or read lock bit status command is being executed; otherwise,
it is set to 1.
The MCU can accept commands when the FMR01 bit is set to 1 (CPU rewrite mode). Set the FMR05 bit
to 1 (user ROM area access) as well if in boot mode.
The lock bit is disabled by setting the FMR02 bit to 1 (lock bit disabled). (Refer to 21.3.6 Data Protect
Function.) The lock bit is enabled by setting the FMR02 bit to 0 (lock bit enabled).
The FMR02 bit does not change the lock bit status but disables the lock bit function. If the block erase or
erase all unlocked block command is executed when the FMR02 bit is set to 1, the lock bit status
changes 0 (locked) to 1 (unlocked) after command execution is completed.
The FMSTP bit resets the flash memory control circuits and minimizes power consumption in the flash
memory. Access to the flash memory is disabled when the FMSTP bit is set to 1 (flash memory operation
stops). Set the FMSTP bit by program in a space other than the flash memory.
Set the FMSTP bit to 1 if one of the followings occurs:
• A flash memory access error occurs while erasing or programming in EW0 mode (FMR00 bit does not
• Low power dissipation mode or on-chip oscillator low power dissipation mode is entered
Use the following the procedure to change the FMSTP bit setting.
Figure 21.7 shows the Processing Before and After Low Power Dissipation Mode or On-chip Oscillator
Low Power Dissipation Mode. Follow the procedure on this flow chart.
When entering stop or wait mode, the flash memory is automatically turned off. When exiting stop or wait
mode, the flash memory is turned back on. The FMR0 register does not need to be set.
This bit selects the boot ROM or user ROM area in boot mode. Set to 0 to access (read) the boot ROM
area or to 1 (user ROM access) to access (read, write or erase) the user ROM area.
This is a read-only bit indicating the status of an auto-program operation. The FMR06 bit is set to 1 when
a program error occurs; otherwise, it is set to 0. Refer to 21.3.8 Full Status Check.
switch back to 1 (ready))
(1) Set the FMSTP bit to 1
(2) Set tps (the wait time to stabilize flash memory circuit)
(3) Set the FMSTP bit to 0
(4) Set tps (the wait time to stabilize flash memory circuit)
Apr 14, 2006
page 258 of 376
21. Flash Memory Version