M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 404

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.00 Nov. 10, 2004
Rev.
Date
REVISION HISTORY
140, 141 Figures 15.1 to 15.3 UART0 to 2 Block Diagram are revised.
Page
134
135
136
137
139
142
144
145
153
154
156
157
159
161
162
164
176
179
181
189
205
206
209
216
217
218
Figure 14.6 (upper) ICTB2 Register
Figure 14.7 (upper) TRGSR Register: NOTE 2 is added.
Figure 14.8 (upper) TA1MR, TA2MR and TA4MR Registers
Figure 14.9 Triangular Wave Modulation Operation is revised.
15.1 UARTi: "UART0, UART1" in Special mode 3 is deleted.
Figure 15.4 UARTi Transmit/Receive Unit is revised.
Figure 15.6 (lower) U0C0 to U2C0 Registers: NOTES 3, 4 are revised.
Figure 15.7 (upper) U0C1, U1C1 Registers
Figure 15.7 (lower) U2C1 Register: NOTE 1 is added.
15.1.1.1 Counter Measure for Communication Error Occurs is added.
15.1.1.4 Continuous Receive Mode: first to 4th lines are added.
15.1.1.7 CTS/RTS Function is added.
Table 15.5 UART Mode Specifications: NOTE 3 is added.
Table 15.7 I/O Pin Functions
15.1.2.1 Bit Rates and Table 15.9 Example of Bit Rates and Settings are added.
15.1.2.2 Counter Measure for Communication Error Occurs is added.
15.1.2.6 CTS/RTS Function is added.
Table 15.15 Registers to Be Used and Settings in Special Mode 2
Table 15.16 Registers to Be Used and Settings in IE Mode
Table 15.17 SIM Mode Specifications: NOTE 3 is added.
Figure 15.39 Polarity of Transfer Clock is revised.
16.2.4 External Operation Amplifier (Op-Amp) Connection Mode: 6th line
16.2.6 Output Impedance of Sensor under A/D Conversion is added.
Figure 17.2 (lower) DA0 and DA1 Registers: The value of After Reset are revised.
Figure 19.4 Bit Mapping of Mask Registers in Byte Access: NOTES 1, 2 are added.
Figure 19.5 Bit Mapping of Mask Registers in Word Access: NOTES 1, 2 are added.
Figure 19.6 C0MCTLj and C1MCTLj Registers: NOTE 2 is revised.
Figure 19.7 C0CTLR and C1CTLR Registers (upper)
Figure 19.7 C0CTLR and C1CTLR Registers (lower): NOTES 3, 4 are added.
• (b7-b4) is revised.
• NOTE 3 is added.
• Function of MR1 bit: "Has no effect" is revised to "Set to "0" ".
• The value of After Reset is revised.
• (b5-b4) is revised from "When read, their contents are "0" " to "When read, their
• NOTE 1 is added.
• Method of Selection in TXDi: "Output dummy data" is revised to "Output "H" ".
• "U2LCH" in UiC1 register is revised to "UiLCH".
• "UiRRM" in UiC1 register is revised to "U2RRM".
• "Note that the ANEX0 and ANEX1 pins cannot be directly connected to each other."
• NOTE 1 (Rev.1.00) is deleted and NOTES 1, 2, 3 are added.
contents are indeterminate".
is deleted.
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M16C/6N Group (M16C/6N4) Hardware Manual
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Description
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