M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 197

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 15.26 STSPSEL Bit Functions
Table 15.13 STSPSEL Bit Functions
Output of pins SCLi and SDAi
Start/stop condition interrupt
request generation timing
15.1.3.3 Arbitration
Unmatching of the transmit data and SDAi pin input data is checked synchronously with the rising edge
of SCLi. Use the ABC bit in the UiSMR register to select the timing at which the ABT bit in the UiRB
register is updated. If the ABC bit = 0 (updated per bit), the ABT bit is set to 1 at the same time
unmatching is detected during check, and is set to 0 when not detected. In cases when the ABC bit is set
to 1, if unmatching is detected even once during check, the ABT bit is set to 1 (unmatching detected) at
the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be updated per byte, set the ABT bit
to 0 (undetected) after detecting acknowledge in the first byte, before transferring the next byte.
Setting the ALS bit in the UiSMR2 register to 1 (SDA output stop enabled) causes arbitration-lost to
occur, in which case the SDAi pin is placed in the high-impedance state at the same time the ABT bit is
set to 1 (unmatching detected).
Apr 14, 2006
(2) When master
(1) When slave
Function
SDAi
STSPSEL bit
SCLi
SDAi
CKDIR bit = 0 (internal clock), CKPH bit = 1 (clock delayed)
STSPSEL bit
SCLi
CKDIR bit = 1 (external clock)
page 173 of 376
Set STAREQ bit
= 1 (start)
0
Start condition
detection interrupt
Set to 1 in
a program
Output of transfer clock and
data
Output of start/stop condition is
accomplished by a program
using ports (not automatically
generated in hardware)
Start/stop condition detection
Start condition
detection interrupt
1st 2nd 3rd 4th
Set to 0 in
a program
STSPSEL Bit = 0
1st 2nd 3rd 4th
5th
6th 7th 8th
5th
Set STPREQ bit
= 1 (start)
6th 7th 8th
Stop condition
detection interrupt
9th bit
Output of a start/stop condition
depending on bits STAREQ,
RSTAREQ, and STPREQ
Finish generating start/stop
condition
Set to 1 in
a program
9th bit
Stop condition
detection interrupt
STSPSEL Bit = 1
Set to 0 in
a program
15. Serial Interface